FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators
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arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866916098005270528 |
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| author | Dhingra, Pratyush Ogbogu, Chukwufumnanya Joardar, Biresh Kumar Doppa, Janardhan Rao Kalyanaraman, Ananth Pande, Partha Pratim |
| author_facet | Dhingra, Pratyush Ogbogu, Chukwufumnanya Joardar, Biresh Kumar Doppa, Janardhan Rao Kalyanaraman, Ananth Pande, Partha Pratim |
| contents | Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture is an attractive solution for training Graph Neural Networks (GNNs) on edge platforms. However, the immature fabrication process and limited write endurance of ReRAMs make them prone to hardware faults, thereby limiting their widespread adoption for GNN training. Further, the existing fault-tolerant solutions prove inadequate for effectively training GNNs in the presence of faults. In this paper, we propose a fault-aware framework referred to as FARe that mitigates the effect of faults during GNN training. FARe outperforms existing approaches in terms of both accuracy and timing overhead. Experimental results demonstrate that FARe framework can restore GNN test accuracy by 47.6% on faulty ReRAM hardware with a ~1% timing overhead compared to the fault-free counterpart. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2401_10522 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators Dhingra, Pratyush Ogbogu, Chukwufumnanya Joardar, Biresh Kumar Doppa, Janardhan Rao Kalyanaraman, Ananth Pande, Partha Pratim Hardware Architecture Machine Learning B.8.1 Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture is an attractive solution for training Graph Neural Networks (GNNs) on edge platforms. However, the immature fabrication process and limited write endurance of ReRAMs make them prone to hardware faults, thereby limiting their widespread adoption for GNN training. Further, the existing fault-tolerant solutions prove inadequate for effectively training GNNs in the presence of faults. In this paper, we propose a fault-aware framework referred to as FARe that mitigates the effect of faults during GNN training. FARe outperforms existing approaches in terms of both accuracy and timing overhead. Experimental results demonstrate that FARe framework can restore GNN test accuracy by 47.6% on faulty ReRAM hardware with a ~1% timing overhead compared to the fault-free counterpart. |
| title | FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators |
| topic | Hardware Architecture Machine Learning B.8.1 |
| url | https://arxiv.org/abs/2401.10522 |