APA (7th ed.) Citation

Ferry, C., Derumigny, N., Derrien, S., & Rajopadhye, S. (2024). An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators.

Chicago Style (17th ed.) Citation

Ferry, Corentin, Nicolas Derumigny, Steven Derrien, and Sanjay Rajopadhye. An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. 2024.

MLA (9th ed.) Citation

Ferry, Corentin, et al. An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. 2024.