An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866916101732958208 |
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| author | Ferry, Corentin Derumigny, Nicolas Derrien, Steven Rajopadhye, Sanjay |
| author_facet | Ferry, Corentin Derumigny, Nicolas Derrien, Steven Rajopadhye, Sanjay |
| contents | Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve the efficiency of transfers. This paper addresses the later issue by proposing (i) a compiler-based approach to accelerator's data layout to maximize contiguous access to off-chip memory, and (ii) data packing and runtime compression techniques that take advantage of this layout to further improve memory performance. We show that our approach can decrease the I/O cycles up to $7\times$ compared to un-optimized memory accesses. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2401_12071 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators Ferry, Corentin Derumigny, Nicolas Derrien, Steven Rajopadhye, Sanjay Hardware Architecture Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve the efficiency of transfers. This paper addresses the later issue by proposing (i) a compiler-based approach to accelerator's data layout to maximize contiguous access to off-chip memory, and (ii) data packing and runtime compression techniques that take advantage of this layout to further improve memory performance. We show that our approach can decrease the I/O cycles up to $7\times$ compared to un-optimized memory accesses. |
| title | An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2401.12071 |