A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN
Fuente:
arXiv
Saved in:
| Main Authors: | Khandelwal, Shashwat, Shanker, Shreejith |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
SecCAN: An Extended CAN Controller with Embedded Intrusion Detection
by: Khandelwal, Shashwat, et al.
Published: (2025)
by: Khandelwal, Shashwat, et al.
Published: (2025)
A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAs
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
Real-Time Zero-Day Intrusion Detection System for Automotive Controller Area Network on FPGAs
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies
by: Li, Changhong, et al.
Published: (2025)
by: Li, Changhong, et al.
Published: (2025)
Deep Learning-based Embedded Intrusion Detection System for Automotive CAN
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
by: Foudhaili, Wadid, et al.
Published: (2024)
by: Foudhaili, Wadid, et al.
Published: (2024)
Space-Control: Process-Level Isolation for Sharing CXL-based Disaggregated Memory
by: Goswami, Kaustav, et al.
Published: (2026)
by: Goswami, Kaustav, et al.
Published: (2026)
FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs
by: Khandelwal, Shashwat, et al.
Published: (2025)
by: Khandelwal, Shashwat, et al.
Published: (2025)
PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems
by: Swaroopa, Sneha, et al.
Published: (2025)
by: Swaroopa, Sneha, et al.
Published: (2025)
Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators
by: Weerasena, Hansika, et al.
Published: (2023)
by: Weerasena, Hansika, et al.
Published: (2023)
Thales: Formulating and Estimating Architectural Vulnerability Factors for DNN Accelerators
by: Tyagi, Abhishek, et al.
Published: (2022)
by: Tyagi, Abhishek, et al.
Published: (2022)
Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)
by: Ajmi, Hala, et al.
Published: (2022)
NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction
by: Das, Voktho, et al.
Published: (2026)
by: Das, Voktho, et al.
Published: (2026)
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
by: Castelino, Cornell, et al.
Published: (2024)
by: Castelino, Cornell, et al.
Published: (2024)
Attack on a PUF-based Secure Binary Neural Network
by: Basak, Bijeet, et al.
Published: (2025)
by: Basak, Bijeet, et al.
Published: (2025)
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2022)
by: Olgun, Ataberk, et al.
Published: (2022)
Logistic Map Pseudo Random Number Generator in FPGA
by: Calderon, Mateo Jalen Andrew, et al.
Published: (2024)
by: Calderon, Mateo Jalen Andrew, et al.
Published: (2024)
REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)
by: Baddour, Yazan, et al.
Published: (2025)
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs
by: Butt, Shahzad Ahmad, et al.
Published: (2024)
by: Butt, Shahzad Ahmad, et al.
Published: (2024)
FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)
by: Xu, Zhihan, et al.
Published: (2025)
DARTH-PUM: A Hybrid Processing-Using-Memory Architecture
by: Wong, Ryan, et al.
Published: (2026)
by: Wong, Ryan, et al.
Published: (2026)
SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators
by: Afifi, Salma, et al.
Published: (2024)
by: Afifi, Salma, et al.
Published: (2024)
DL2Fence: Integrating Deep Learning and Frame Fusion for Enhanced Detection and Localization of Refined Denial-of-Service in Large-Scale NoCs
by: Wang, Haoyu, et al.
Published: (2024)
by: Wang, Haoyu, et al.
Published: (2024)
Evasive Hardware Trojan through Adversarial Power Trace
by: Omidi, Behnam, et al.
Published: (2024)
by: Omidi, Behnam, et al.
Published: (2024)
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)
by: Wang, Fangzhou, et al.
Published: (2024)
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)
by: Wang, Zeng, et al.
Published: (2024)
FedBit: Accelerating Privacy-Preserving Federated Learning via Bit-Interleaved Packing and Cross-Layer Co-Design
by: Meng, Xiangchen, et al.
Published: (2025)
by: Meng, Xiangchen, et al.
Published: (2025)
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
Bit-Flip Vulnerability of Shared KV-Cache Blocks in LLM Serving Systems
by: Yamamoto, Yuji, et al.
Published: (2026)
by: Yamamoto, Yuji, et al.
Published: (2026)
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)
by: Knechtel, Johann, et al.
Published: (2026)
Tessera: Secure, Near-Line-Rate Weight Streaming for UMA Edge Accelerators
by: Naskar, Animan
Published: (2026)
by: Naskar, Animan
Published: (2026)
Breaking On-Chip Communication Anonymity using Flow Correlation Attacks
by: Weerasena, Hansika, et al.
Published: (2023)
by: Weerasena, Hansika, et al.
Published: (2023)
2-in-1 Accelerator: Enabling Random Precision Switch for Winning Both Adversarial Robustness and Efficiency
by: Fu, Yonggan, et al.
Published: (2021)
by: Fu, Yonggan, et al.
Published: (2021)
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
IMS: Intelligent Hardware Monitoring System for Secure SoCs
by: Foudhaili, Wadid, et al.
Published: (2026)
by: Foudhaili, Wadid, et al.
Published: (2026)
μRL: Discovering Transient Execution Vulnerabilities Using Reinforcement Learning
by: Tol, M. Caner, et al.
Published: (2025)
by: Tol, M. Caner, et al.
Published: (2025)
Cocoon: A System Architecture for Differentially Private Training with Correlated Noises
by: Kim, Donghwan, et al.
Published: (2025)
by: Kim, Donghwan, et al.
Published: (2025)
Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
by: Kumari, Ruby, et al.
Published: (2025)
by: Kumari, Ruby, et al.
Published: (2025)
Similar Items
-
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
by: Khandelwal, Shashwat, et al.
Published: (2024) -
Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks
by: Khandelwal, Shashwat, et al.
Published: (2024) -
SecCAN: An Extended CAN Controller with Embedded Intrusion Detection
by: Khandelwal, Shashwat, et al.
Published: (2025) -
A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAs
by: Khandelwal, Shashwat, et al.
Published: (2024) -
Real-Time Zero-Day Intrusion Detection System for Automotive Controller Area Network on FPGAs
by: Khandelwal, Shashwat, et al.
Published: (2024)