A modular architecture for IMU-based data gloves
Fuente:
arXiv
Saved in:
| Main Authors: | Carfì, Alessandro, Alameh, Mohamad, Belcamino, Valerio, Mastrogiovanni, Fulvio |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
A Systematic Review on Custom Data Gloves
by: Belcamino, Valerio, et al.
Published: (2024)
by: Belcamino, Valerio, et al.
Published: (2024)
A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
Memristor Technologies for Dynamic Vision Sensors: A Critical Assessment and Research Roadmap
by: Sadoun, Mohamad Yazan, et al.
Published: (2026)
by: Sadoun, Mohamad Yazan, et al.
Published: (2026)
The Bicameral Cache: a split cache for vector architectures
by: Rebolledo, Susana, et al.
Published: (2024)
by: Rebolledo, Susana, et al.
Published: (2024)
Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
by: Nayan, Md Mizanur Rahaman, et al.
Published: (2025)
by: Nayan, Md Mizanur Rahaman, et al.
Published: (2025)
CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
ABI: A tightly integrated, unified, sparsity-aware, reconfigurable, compute near-register file/cache GPU architecture with light-weight softmax for deep learning, linear algebra, and Ising compute
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis
by: Raj, Ritik, et al.
Published: (2025)
by: Raj, Ritik, et al.
Published: (2025)
A Memory-Efficient Retrieval Architecture for RAG-Enabled Wearable Medical LLMs-Agents
by: Liao, Zhipeng, et al.
Published: (2025)
by: Liao, Zhipeng, et al.
Published: (2025)
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
by: Ottaviano, Alessandro, et al.
Published: (2023)
by: Ottaviano, Alessandro, et al.
Published: (2023)
GeneTEK: Low-power, high-performance and scalable FPGA architecture for exact unit-cost edit distance
by: Espinosa, Elena, et al.
Published: (2025)
by: Espinosa, Elena, et al.
Published: (2025)
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
by: Reinwardt, Christopher, et al.
Published: (2025)
by: Reinwardt, Christopher, et al.
Published: (2025)
Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring
by: Liang, Chaoqun, et al.
Published: (2025)
by: Liang, Chaoqun, et al.
Published: (2025)
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
by: Benz, Thomas, et al.
Published: (2025)
by: Benz, Thomas, et al.
Published: (2025)
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
by: Ottaviano, Alessandro, et al.
Published: (2024)
by: Ottaviano, Alessandro, et al.
Published: (2024)
Enhancing software-hardware co-design for HEP by low-overhead profiling of single- and multi-threaded programs on diverse architectures with Adaptyst
by: Graczyk, Maksymilian, et al.
Published: (2025)
by: Graczyk, Maksymilian, et al.
Published: (2025)
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
by: Liang, Chaoqun, et al.
Published: (2024)
by: Liang, Chaoqun, et al.
Published: (2024)
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
by: Rogenmoser, Michael, et al.
Published: (2024)
by: Rogenmoser, Michael, et al.
Published: (2024)
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
by: Riedel, Samuel, et al.
Published: (2024)
by: Riedel, Samuel, et al.
Published: (2024)
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
by: Bertuletti, Marco, et al.
Published: (2026)
by: Bertuletti, Marco, et al.
Published: (2026)
A Review of SRAM-based Compute-in-Memory Circuits
by: Yoshioka, Kentaro, et al.
Published: (2024)
by: Yoshioka, Kentaro, et al.
Published: (2024)
Hardware and software build flow with SoCMake
by: Pejašinović, Risto, et al.
Published: (2025)
by: Pejašinović, Risto, et al.
Published: (2025)
SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis
by: Shao, Kunming, et al.
Published: (2024)
by: Shao, Kunming, et al.
Published: (2024)
Design high-confidence computers using trusted instructional set architecture and emulators
by: Wang, Shuangbao Paul
Published: (2025)
by: Wang, Shuangbao Paul
Published: (2025)
AxLLM: accelerator architecture for large language models with computation reuse capability
by: Ahadi, Soroush, et al.
Published: (2025)
by: Ahadi, Soroush, et al.
Published: (2025)
Scalable data concentrator with baseline interconnection network for triggerless data acquisition systems
by: Zabołotny, Wojciech M.
Published: (2023)
by: Zabołotny, Wojciech M.
Published: (2023)
SAL-PIM: A Subarray-level Processing-in-Memory Architecture with LUT-based Linear Interpolation for Transformer-based Text Generation
by: Han, Wontak, et al.
Published: (2024)
by: Han, Wontak, et al.
Published: (2024)
ApproxPilot: A GNN-based Accelerator Approximation Framework
by: Zhang, Qing, et al.
Published: (2024)
by: Zhang, Qing, et al.
Published: (2024)
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
by: Zelioli, Enrico, et al.
Published: (2024)
by: Zelioli, Enrico, et al.
Published: (2024)
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
by: Perotti, Matteo, et al.
Published: (2025)
by: Perotti, Matteo, et al.
Published: (2025)
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)
by: Ottaviano, Alessandro, et al.
Published: (2023)
A Survey on LUT-based Deep Neural Networks Implemented in FPGAs
by: Guo, Zeyu
Published: (2025)
by: Guo, Zeyu
Published: (2025)
FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators
by: Isachi, Victor, et al.
Published: (2025)
by: Isachi, Victor, et al.
Published: (2025)
CAMASim: A Comprehensive Simulation Framework for Content-Addressable Memory based Accelerators
by: Li, Mengyuan, et al.
Published: (2024)
by: Li, Mengyuan, et al.
Published: (2024)
A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators
by: Gonul, Yilmaz Ege, et al.
Published: (2025)
by: Gonul, Yilmaz Ege, et al.
Published: (2025)
A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
by: Yang, Junyi, et al.
Published: (2026)
by: Yang, Junyi, et al.
Published: (2026)
FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems
by: Chen, Yiqi, et al.
Published: (2025)
by: Chen, Yiqi, et al.
Published: (2025)
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)
by: Valente, Luca, et al.
Published: (2022)
A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision
by: Choi, Jiwon, et al.
Published: (2024)
by: Choi, Jiwon, et al.
Published: (2024)
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
by: Zhang, Xinmiao, et al.
Published: (2024)
by: Zhang, Xinmiao, et al.
Published: (2024)
Similar Items
-
A Systematic Review on Custom Data Gloves
by: Belcamino, Valerio, et al.
Published: (2024) -
A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026) -
Memristor Technologies for Dynamic Vision Sensors: A Critical Assessment and Research Roadmap
by: Sadoun, Mohamad Yazan, et al.
Published: (2026) -
The Bicameral Cache: a split cache for vector architectures
by: Rebolledo, Susana, et al.
Published: (2024) -
Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
by: Nayan, Md Mizanur Rahaman, et al.
Published: (2025)