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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2024
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| Accès en ligne: | https://arxiv.org/abs/2401.14888 |
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| _version_ | 1866916106662313984 |
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| author | SeyedFaraji, Saeed Bichl, Markus Aftab, Asad Rehman, Semeen |
| author_facet | SeyedFaraji, Saeed Bichl, Markus Aftab, Asad Rehman, Semeen |
| contents | Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture. But there is a lack of available open-source STT-RAM-based system evaluation framework, which hampers research and experimentation and impacts the adoption of STT- RAM in a system. This paper proposes a novel, extendable STT-RAM memory controller design integrated inside the gem5 simulator. Our framework enables understanding various aspects of STT-RAM, i.e., power, delay, clock cycles, energy, and system throughput. We will open-source our HOPE framework, which will fuel research and aid in accelerating the development of future system architectures based on STT-RAM. It will also facilitate the user for further tool enhancement. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2401_14888 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis SeyedFaraji, Saeed Bichl, Markus Aftab, Asad Rehman, Semeen Hardware Architecture Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile Memory (NVM) technology that has garnered attention to overcome the drawbacks of conventional CMOS-based technologies. However, such technologies must be evaluated before deployment under real workloads and architecture. But there is a lack of available open-source STT-RAM-based system evaluation framework, which hampers research and experimentation and impacts the adoption of STT- RAM in a system. This paper proposes a novel, extendable STT-RAM memory controller design integrated inside the gem5 simulator. Our framework enables understanding various aspects of STT-RAM, i.e., power, delay, clock cycles, energy, and system throughput. We will open-source our HOPE framework, which will fuel research and aid in accelerating the development of future system architectures based on STT-RAM. It will also facilitate the user for further tool enhancement. |
| title | HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2401.14888 |