The Design of a High Speed Low Power Phase Locked Loop
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arXiv
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| Format: | Preprint |
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2024
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| _version_ | 1866910311223656448 |
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| author | Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C. Ye, Jingbo |
| author_facet | Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C. Ye, Jingbo |
| contents | The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79-5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2401_16681 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | The Design of a High Speed Low Power Phase Locked Loop Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C. Ye, Jingbo Instrumentation and Detectors The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79-5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented. |
| title | The Design of a High Speed Low Power Phase Locked Loop |
| topic | Instrumentation and Detectors |
| url | https://arxiv.org/abs/2401.16681 |