Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization
Fuente:
arXiv
Guardado en:
| Autores principales: | Tan, Zhanhong, Zhu, Zijian, Ma, Kaisheng |
|---|---|
| Formato: | Preprint |
| Publicado: |
2024
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
por: Feng, Yinxiao, et al.
Publicado: (2022)
por: Feng, Yinxiao, et al.
Publicado: (2022)
SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
por: Cai, Jingwei, et al.
Publicado: (2025)
por: Cai, Jingwei, et al.
Publicado: (2025)
Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration
por: Feng, Yinxiao, et al.
Publicado: (2024)
por: Feng, Yinxiao, et al.
Publicado: (2024)
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
por: Raj, Ritik, et al.
Publicado: (2025)
por: Raj, Ritik, et al.
Publicado: (2025)
CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration
por: Chen, Jinwu, et al.
Publicado: (2026)
por: Chen, Jinwu, et al.
Publicado: (2026)
NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
por: Zhou, Zhe, et al.
Publicado: (2024)
por: Zhou, Zhe, et al.
Publicado: (2024)
Hardware-Software Co-Design for Accelerating Transformer Inference Leveraging Compute-in-Memory
por: Kim, Dong Eun, et al.
Publicado: (2025)
por: Kim, Dong Eun, et al.
Publicado: (2025)
Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference
por: Wang, Xinyu, et al.
Publicado: (2026)
por: Wang, Xinyu, et al.
Publicado: (2026)
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators
por: Das, Abhijit, et al.
Publicado: (2022)
por: Das, Abhijit, et al.
Publicado: (2022)
SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design
por: Zhang, Haoyang, et al.
Publicado: (2025)
por: Zhang, Haoyang, et al.
Publicado: (2025)
QED: Scalable Verification of Hardware Memory Consistency
por: Ravi, Gokulan, et al.
Publicado: (2024)
por: Ravi, Gokulan, et al.
Publicado: (2024)
In-Memory Computing Architecture for Efficient Hardware Security
por: Ajmi, Hala, et al.
Publicado: (2024)
por: Ajmi, Hala, et al.
Publicado: (2024)
FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators
por: Abarajithan, G, et al.
Publicado: (2026)
por: Abarajithan, G, et al.
Publicado: (2026)
METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
por: Wang, Zhao, et al.
Publicado: (2021)
por: Wang, Zhao, et al.
Publicado: (2021)
SD-Acc: Accelerating Stable Diffusion through Phase-aware Sampling and Hardware Co-Optimizations
por: Wang, Zhican, et al.
Publicado: (2025)
por: Wang, Zhican, et al.
Publicado: (2025)
Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
por: Zou, Yuyang, et al.
Publicado: (2025)
por: Zou, Yuyang, et al.
Publicado: (2025)
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
por: You, Dean, et al.
Publicado: (2025)
por: You, Dean, et al.
Publicado: (2025)
HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
por: Zhang, Yipu, et al.
Publicado: (2025)
por: Zhang, Yipu, et al.
Publicado: (2025)
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
por: Ghosh, Arkapravo, et al.
Publicado: (2025)
por: Ghosh, Arkapravo, et al.
Publicado: (2025)
Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
por: Wang, Chuanzhen, et al.
Publicado: (2026)
por: Wang, Chuanzhen, et al.
Publicado: (2026)
Hardware-based Heterogeneous Memory Management for Large Language Model Inference
por: Hwang, Soojin, et al.
Publicado: (2025)
por: Hwang, Soojin, et al.
Publicado: (2025)
GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
por: Eudine, Julien, et al.
Publicado: (2026)
por: Eudine, Julien, et al.
Publicado: (2026)
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
por: Ye, Haojie, et al.
Publicado: (2024)
por: Ye, Haojie, et al.
Publicado: (2024)
Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
por: Li, Boyu, et al.
Publicado: (2025)
por: Li, Boyu, et al.
Publicado: (2025)
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
por: Geens, Robin, et al.
Publicado: (2026)
por: Geens, Robin, et al.
Publicado: (2026)
GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
por: Lu, Tsung-Han, et al.
Publicado: (2026)
por: Lu, Tsung-Han, et al.
Publicado: (2026)
ANCoEF: Asynchronous Neuromorphic Algorithm/Hardware Co-Exploration Framework with a Fully Asynchronous Simulator
por: Zhang, Jian, et al.
Publicado: (2024)
por: Zhang, Jian, et al.
Publicado: (2024)
Educating for Hardware Specialization in the Chiplet Era: A Path for the HPC Community
por: Yoshii, Kazutomo, et al.
Publicado: (2024)
por: Yoshii, Kazutomo, et al.
Publicado: (2024)
LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration
por: Vungarala, Deepak, et al.
Publicado: (2025)
por: Vungarala, Deepak, et al.
Publicado: (2025)
AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
por: Xue, Chenhao, et al.
Publicado: (2026)
por: Xue, Chenhao, et al.
Publicado: (2026)
Limited Read-Write/Set Hardware Transactional Memory without modifying the ISA or the Coherence Protocol
por: Kafousis, Konstantinos
Publicado: (2025)
por: Kafousis, Konstantinos
Publicado: (2025)
Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-aware Cache Compression
por: Cheng, Feng, et al.
Publicado: (2025)
por: Cheng, Feng, et al.
Publicado: (2025)
Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs
por: Chowdhury, Md Rownak Hossain, et al.
Publicado: (2025)
por: Chowdhury, Md Rownak Hossain, et al.
Publicado: (2025)
Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator
por: Li, Cong, et al.
Publicado: (2026)
por: Li, Cong, et al.
Publicado: (2026)
PIM-FW: Hardware-Software Co-Design of All-pairs Shortest Paths in DRAM
por: Lu, Tsung-Han, et al.
Publicado: (2025)
por: Lu, Tsung-Han, et al.
Publicado: (2025)
Inclusive-PIM: Hardware-Software Co-design for Broad Acceleration on Commercial PIM Architectures
por: Alsop, Johnathan, et al.
Publicado: (2023)
por: Alsop, Johnathan, et al.
Publicado: (2023)
CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware
por: Kundu, Souvik, et al.
Publicado: (2024)
por: Kundu, Souvik, et al.
Publicado: (2024)
Hardware Memory Management for Future Mobile Hybrid Memory Systems
por: Wen, Fei, et al.
Publicado: (2020)
por: Wen, Fei, et al.
Publicado: (2020)
Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA
por: Li, Jindong, et al.
Publicado: (2025)
por: Li, Jindong, et al.
Publicado: (2025)
MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator
por: He, Xiaolin, et al.
Publicado: (2025)
por: He, Xiaolin, et al.
Publicado: (2025)
Ejemplares similares
-
Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
por: Feng, Yinxiao, et al.
Publicado: (2022) -
SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
por: Cai, Jingwei, et al.
Publicado: (2025) -
Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration
por: Feng, Yinxiao, et al.
Publicado: (2024) -
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
por: Raj, Ritik, et al.
Publicado: (2025) -
CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration
por: Chen, Jinwu, et al.
Publicado: (2026)