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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2402.06520 |
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| _version_ | 1866916382353915904 |
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| author | Engelhardt, Maximilian Giehl, Sebastian Schubert, Michael Ihlow, Alexander Schneider, Christian Ebert, Alexander Landmann, Markus Del Galdo, Giovanni Andrich, Carsten |
| author_facet | Engelhardt, Maximilian Giehl, Sebastian Schubert, Michael Ihlow, Alexander Schneider, Christian Ebert, Alexander Landmann, Markus Del Galdo, Giovanni Andrich, Carsten |
| contents | The upcoming 3GPP global mobile communication standard 6G strives to push the technological limits of radio frequency (RF) communication even further than its predecessors: Sum data rates beyond 100 Gbit/s, RF bandwidths above 1 GHz per link, and sub-millisecond latency necessitate very high performance development tools. We propose a new SDR firmware and software architecture designed explicitly to meet these challenging requirements. It relies on Ethernet and commercial off-the-shelf network and server components to maximize flexibility and to reduce costs. We analyze state-of-the-art solutions (USRP X440 and other RFSoC-based systems), derive architectural design goals, explain resulting design decision in detail, and exemplify our architecture's implementation on the XCZU48DR RFSoC. Finally, we validate its performance via measurements and outline how the architecture surpasses the state-of-the-art with respect to sustained RF recording, while maintaining high Ethernet bandwidth efficiency. Building a 6G integrated sensing and communication (ISAC) example, we demonstrate its real-time and rapid application development capabilities. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2402_06520 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Accelerating Innovation in 6G Research: Real-Time Capable SDR System Architecture for Rapid Prototyping Engelhardt, Maximilian Giehl, Sebastian Schubert, Michael Ihlow, Alexander Schneider, Christian Ebert, Alexander Landmann, Markus Del Galdo, Giovanni Andrich, Carsten Signal Processing The upcoming 3GPP global mobile communication standard 6G strives to push the technological limits of radio frequency (RF) communication even further than its predecessors: Sum data rates beyond 100 Gbit/s, RF bandwidths above 1 GHz per link, and sub-millisecond latency necessitate very high performance development tools. We propose a new SDR firmware and software architecture designed explicitly to meet these challenging requirements. It relies on Ethernet and commercial off-the-shelf network and server components to maximize flexibility and to reduce costs. We analyze state-of-the-art solutions (USRP X440 and other RFSoC-based systems), derive architectural design goals, explain resulting design decision in detail, and exemplify our architecture's implementation on the XCZU48DR RFSoC. Finally, we validate its performance via measurements and outline how the architecture surpasses the state-of-the-art with respect to sustained RF recording, while maintaining high Ethernet bandwidth efficiency. Building a 6G integrated sensing and communication (ISAC) example, we demonstrate its real-time and rapid application development capabilities. |
| title | Accelerating Innovation in 6G Research: Real-Time Capable SDR System Architecture for Rapid Prototyping |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2402.06520 |