Accelerating Sparse DNNs Based on Tiled GEMM
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866910334235705344 |
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| author | Guo, Cong Xue, Fengchen Leng, Jingwen Qiu, Yuxian Guan, Yue Cui, Weihao Chen, Quan Guo, Minyi |
| author_facet | Guo, Cong Xue, Fengchen Leng, Jingwen Qiu, Yuxian Guan, Yue Cui, Weihao Chen, Quan Guo, Minyi |
| contents | Network pruning can reduce the computation cost of deep neural network (DNN) models. However, sparse models often produce randomly-distributed weights to maintain accuracy, leading to irregular computations. Consequently, unstructured sparse models cannot achieve meaningful speedup on commodity hardware built for dense matrix computations. Accelerators are usually modified or designed with structured sparsity-optimized architectures for exploiting sparsity. For example, the Ampere architecture introduces a sparse tensor core, which adopts the 2:4 sparsity pattern.
We propose a pruning method that builds upon the insight that matrix multiplication generally breaks the large matrix into multiple smaller tiles for parallel execution. We present the tile-wise sparsity pattern, which maintains a structured sparsity pattern at the tile level for efficient execution but allows for irregular pruning at the global scale to maintain high accuracy. In addition, the tile-wise sparsity is implemented at the global memory level, and the 2:4 sparsity executes at the register level inside the sparse tensor core. We can combine these two patterns into a tile-vector-wise (TVW) sparsity pattern to explore more fine-grained sparsity and further accelerate the sparse DNN models. We evaluate the TVW on the GPU, achieving averages of $1.85\times$, $2.75\times$, and $22.18\times$ speedups over the dense model, block sparsity, and unstructured sparsity. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2402_10876 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Accelerating Sparse DNNs Based on Tiled GEMM Guo, Cong Xue, Fengchen Leng, Jingwen Qiu, Yuxian Guan, Yue Cui, Weihao Chen, Quan Guo, Minyi Distributed, Parallel, and Cluster Computing Network pruning can reduce the computation cost of deep neural network (DNN) models. However, sparse models often produce randomly-distributed weights to maintain accuracy, leading to irregular computations. Consequently, unstructured sparse models cannot achieve meaningful speedup on commodity hardware built for dense matrix computations. Accelerators are usually modified or designed with structured sparsity-optimized architectures for exploiting sparsity. For example, the Ampere architecture introduces a sparse tensor core, which adopts the 2:4 sparsity pattern. We propose a pruning method that builds upon the insight that matrix multiplication generally breaks the large matrix into multiple smaller tiles for parallel execution. We present the tile-wise sparsity pattern, which maintains a structured sparsity pattern at the tile level for efficient execution but allows for irregular pruning at the global scale to maintain high accuracy. In addition, the tile-wise sparsity is implemented at the global memory level, and the 2:4 sparsity executes at the register level inside the sparse tensor core. We can combine these two patterns into a tile-vector-wise (TVW) sparsity pattern to explore more fine-grained sparsity and further accelerate the sparse DNN models. We evaluate the TVW on the GPU, achieving averages of $1.85\times$, $2.75\times$, and $22.18\times$ speedups over the dense model, block sparsity, and unstructured sparsity. |
| title | Accelerating Sparse DNNs Based on Tiled GEMM |
| topic | Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2402.10876 |