Cover Image

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Torrens, Gabriel, de Paul, Ivan, Alorda, Bartomeu, Bota, Sebastia, Segura, Jaume
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
by: Alorda, Bartomeu, et al.
Published: (2024)

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
by: Torrens, Gabriel, et al.
Published: (2024)

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
by: Malagon, Daniel, et al.
Published: (2024)

Estimation during Design Phases of Suitable SRAM Cells for PUF Applications Using Separatrix and Mismatch Metrics
by: Alheyasat, Abdel, et al.
Published: (2024)

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram
by: Torrens, Gabriel, et al.
Published: (2024)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
by: Duan, Cenlin, et al.
Published: (2024)

Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells
by: Van Brandt, Léopold, et al.
Published: (2024)

SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
by: Shen, Shan, et al.
Published: (2024)

CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures
by: Qi, Yingjie, et al.
Published: (2025)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)

A Review of SRAM-based Compute-in-Memory Circuits
by: Yoshioka, Kentaro, et al.
Published: (2024)

Accelerating Seed Location Filtering in DNA Read Mapping Using a Commercial Compute-in-SRAM Architecture
by: Golden, Courtney, et al.
Published: (2024)

CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)

AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
by: Xue, Chenhao, et al.
Published: (2026)

Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection
by: Shen, Shan, et al.
Published: (2023)

A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells
by: Dizabadi, Naser Khatti, et al.
Published: (2026)

OpenACM: An Open-Source SRAM-Based Approximate CiM Compiler
by: Zhou, Yiqi, et al.
Published: (2026)

SAIL: SRAM-Accelerated LLM Inference System with Lookup-Table-based GEMV
by: Zhang, Jingyao, et al.
Published: (2025)

OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite
by: Shen, Shan, et al.
Published: (2025)

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
by: Souvatzoglou, Ioanna, et al.
Published: (2024)

GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
by: Chakraborty, Subhradip, et al.
Published: (2026)

OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs
by: Seyedfaraji, Saeed, et al.
Published: (2024)

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
by: M, Amogh K, et al.
Published: (2025)

SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware
by: Dhakad, Narendra Singh, et al.
Published: (2026)

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
by: Duan, Cenlin, et al.
Published: (2025)

CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration
by: Ahn, Bas, et al.
Published: (2026)

TRAPTI: Time-Resolved Analysis for SRAM Banking and Power Gating Optimization in Embedded Transformer Inference
by: Klhufek, Jan, et al.
Published: (2026)

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
by: Zhang, Wenlun, et al.
Published: (2024)

Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference
by: Liu, Yiqi, et al.
Published: (2026)

Latch Based Design for Fast Voltage Droop Response
by: Srinivas, Shreyas, et al.
Published: (2025)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)

VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
by: Ahmed, Akram Ben, et al.
Published: (2026)

Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device
by: Zhang, Niansong, et al.
Published: (2025)

CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration
by: Chen, Jinwu, et al.
Published: (2026)

A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
by: Kao, Shih-Hang, et al.
Published: (2026)

A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement
by: Gomi, Yuibi, et al.
Published: (2025)

TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations
by: Wang, Dengfeng, et al.
Published: (2023)

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
by: Sonnino, Lorenzo, et al.
Published: (2023)

Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
by: Shen, Shan, et al.
Published: (2025)

ShortCircuit: AlphaZero-Driven Circuit Design
by: Tsaras, Dimitrios, et al.
Published: (2024)