Cover Image

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Eslami, Mohammad, Ghasempouri, Tara, Pagliarini, Samuel
Format:	Preprint
Published:	2024
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
by: Imtiaz, Sharjeel, et al.
Published: (2025)

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
by: Hassan, Muhammad, et al.
Published: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)

iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
by: Elahi, Mehdi, et al.
Published: (2025)

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection
by: Sarihi, Amin, et al.
Published: (2023)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)

TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)

Utilizing Layout Effects for Analog Logic Locking
by: Aljafar, Muayad J., et al.
Published: (2024)

Evasive Hardware Trojan through Adversarial Power Trace
by: Omidi, Behnam, et al.
Published: (2024)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

Modern Hardware Security: A Review of Attacks and Countermeasures
by: Mishra, Jyotiprakash, et al.
Published: (2025)

"vcd2df" -- Leveraging Data Science Insights for Hardware Security Research
by: Deutschbein, Calvin, et al.
Published: (2025)

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation
by: Elahi, Mehdi, et al.
Published: (2024)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
by: Reimann, Lennart M., et al.
Published: (2024)

RowPress Vulnerability in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2024)

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)

RTL2M$μ$PATH: Multi-$μ$PATH Synthesis with Applications to Hardware Security Verification
by: Hsiao, Yao, et al.
Published: (2024)

RowPress: Amplifying Read Disturbance in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2023)

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)

An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2024)

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
by: Bhandari, Jitendra, et al.
Published: (2024)

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
by: Yuksel, Ismail Emir, et al.
Published: (2025)

TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning
by: Sarihi, Amin, et al.
Published: (2024)

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures
by: Weerasena, Hansika, et al.
Published: (2026)

Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
by: Tuğrul, Yahya Can, et al.
Published: (2025)

Bridging the Gap between Hardware Fuzzing and Industrial Verification
by: Ma, Ruiyang, et al.
Published: (2025)

Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption
by: Jeon, Yeonsoo, et al.
Published: (2025)

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
by: Sheikh, Ahmad T., et al.
Published: (2024)

Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)

Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
by: Kim, Jumin, et al.
Published: (2025)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)

IMS: Intelligent Hardware Monitoring System for Secure SoCs
by: Foudhaili, Wadid, et al.
Published: (2026)

Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024)

AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge
by: Ahmed, Anees, et al.
Published: (2024)

An Efficient Algorithm for Modulus Operation and Its Hardware Implementation in Prime Number Calculation
by: Wijesinghe, W. A. Susantha
Published: (2024)