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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2402.14519 |
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| _version_ | 1866916134142345216 |
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| author | Bandla, Kasi Pal, Dipankar |
| author_facet | Bandla, Kasi Pal, Dipankar |
| contents | Strong-ARM Dynamic Latch Comparators are widely used in high-speed analog-to-digital converters (ADCs), sense amplifiers in memory, RFID applications, and data receivers. This paper presents different methods to improve the performance of Strong-Arm latch-based comparators. The comparator's significant features such as power dissipation, propagation delay, offset voltage, clock feedthrough, area, and kickback noises are discussed and compared with state-of-the-art candidate topologies. Simulation results show that the new comparator topologies of Strong-ARM Dynamic Latch proposed by these authors gave the best results. The proposed designs are tested. The simulations are carried out using UMC 180nm double metal, double poly standard CMOS process technology, for a 100 MHz clock, at 1.8V supply-rail on the Cadence Virtuoso EDA platform. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2402_14519 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform Bandla, Kasi Pal, Dipankar Systems and Control Strong-ARM Dynamic Latch Comparators are widely used in high-speed analog-to-digital converters (ADCs), sense amplifiers in memory, RFID applications, and data receivers. This paper presents different methods to improve the performance of Strong-Arm latch-based comparators. The comparator's significant features such as power dissipation, propagation delay, offset voltage, clock feedthrough, area, and kickback noises are discussed and compared with state-of-the-art candidate topologies. Simulation results show that the new comparator topologies of Strong-ARM Dynamic Latch proposed by these authors gave the best results. The proposed designs are tested. The simulations are carried out using UMC 180nm double metal, double poly standard CMOS process technology, for a 100 MHz clock, at 1.8V supply-rail on the Cadence Virtuoso EDA platform. |
| title | Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2402.14519 |