A$^3$PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader
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| Main Authors: | , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866914695972126720 |
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| author | Jiang, Qingcai Tan, Shaojie Chen, Junshi An, Hong |
| author_facet | Jiang, Qingcai Tan, Shaojie Chen, Junshi An, Hong |
| contents | The performance gap between memory and processor has grown rapidly. Consequently, the energy and wall-clock time costs associated with moving data between the CPU and main memory predominate the overall computational cost. The Processing-in-Memory (PIM) paradigm emerges as a promising architecture that mitigates the need for extensive data movements by strategically positioning computing units proximate to the memory. Despite the abundant efforts devoted to building a robust and highly-available PIM system, identifying PIM-friendly segments of applications poses significant challenges due to the lack of a comprehensive tool to evaluate the intrinsic memory access pattern of the segment.
To tackle this challenge, we propose A$^3$PIM: an Automated, Analytic and Accurate Processing-in-Memory offloader. We systematically consider the cross-segment data movement and the intrinsic memory access pattern of each code segment via static code analyzer. We evaluate A$^3$PIM across a wide range of real-world workloads including GAP and PrIM benchmarks and achieve an average speedup of 2.63x and 4.45x (up to 7.14x and 10.64x) when compared to CPU-only and PIM-only executions, respectively. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2402_18592 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A$^3$PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader Jiang, Qingcai Tan, Shaojie Chen, Junshi An, Hong Hardware Architecture Performance The performance gap between memory and processor has grown rapidly. Consequently, the energy and wall-clock time costs associated with moving data between the CPU and main memory predominate the overall computational cost. The Processing-in-Memory (PIM) paradigm emerges as a promising architecture that mitigates the need for extensive data movements by strategically positioning computing units proximate to the memory. Despite the abundant efforts devoted to building a robust and highly-available PIM system, identifying PIM-friendly segments of applications poses significant challenges due to the lack of a comprehensive tool to evaluate the intrinsic memory access pattern of the segment. To tackle this challenge, we propose A$^3$PIM: an Automated, Analytic and Accurate Processing-in-Memory offloader. We systematically consider the cross-segment data movement and the intrinsic memory access pattern of each code segment via static code analyzer. We evaluate A$^3$PIM across a wide range of real-world workloads including GAP and PrIM benchmarks and achieve an average speedup of 2.63x and 4.45x (up to 7.14x and 10.64x) when compared to CPU-only and PIM-only executions, respectively. |
| title | A$^3$PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader |
| topic | Hardware Architecture Performance |
| url | https://arxiv.org/abs/2402.18592 |