Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
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arXiv
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| Autori principali: | , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866913309801840640 |
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| author | Deng, Chenhui Yue, Zichao Yu, Cunxi Sarar, Gokce Carey, Ryan Jain, Rajeev Zhang, Zhiru |
| author_facet | Deng, Chenhui Yue, Zichao Yu, Cunxi Sarar, Gokce Carey, Ryan Jain, Rajeev Zhang, Zhiru |
| contents | While graph neural networks (GNNs) have gained popularity for learning circuit representations in various electronic design automation (EDA) tasks, they face challenges in scalability when applied to large graphs and exhibit limited generalizability to new designs. These limitations make them less practical for addressing large-scale, complex circuit problems. In this work we propose HOGA, a novel attention-based model for learning circuit representations in a scalable and generalizable manner. HOGA first computes hop-wise features per node prior to model training. Subsequently, the hop-wise features are solely used to produce node representations through a gated self-attention module, which adaptively learns important features among different hops without involving the graph topology. As a result, HOGA is adaptive to various structures across different circuits and can be efficiently trained in a distributed manner. To demonstrate the efficacy of HOGA, we consider two representative EDA tasks: quality of results (QoR) prediction and functional reasoning. Our experimental results indicate that (1) HOGA reduces estimation error over conventional GNNs by 46.76% for predicting QoR after logic synthesis; (2) HOGA improves 10.0% reasoning accuracy over GNNs for identifying functional blocks on unseen gate-level netlists after complex technology mapping; (3) The training time for HOGA almost linearly decreases with an increase in computing resources. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_01317 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits Deng, Chenhui Yue, Zichao Yu, Cunxi Sarar, Gokce Carey, Ryan Jain, Rajeev Zhang, Zhiru Machine Learning Hardware Architecture While graph neural networks (GNNs) have gained popularity for learning circuit representations in various electronic design automation (EDA) tasks, they face challenges in scalability when applied to large graphs and exhibit limited generalizability to new designs. These limitations make them less practical for addressing large-scale, complex circuit problems. In this work we propose HOGA, a novel attention-based model for learning circuit representations in a scalable and generalizable manner. HOGA first computes hop-wise features per node prior to model training. Subsequently, the hop-wise features are solely used to produce node representations through a gated self-attention module, which adaptively learns important features among different hops without involving the graph topology. As a result, HOGA is adaptive to various structures across different circuits and can be efficiently trained in a distributed manner. To demonstrate the efficacy of HOGA, we consider two representative EDA tasks: quality of results (QoR) prediction and functional reasoning. Our experimental results indicate that (1) HOGA reduces estimation error over conventional GNNs by 46.76% for predicting QoR after logic synthesis; (2) HOGA improves 10.0% reasoning accuracy over GNNs for identifying functional blocks on unseen gate-level netlists after complex technology mapping; (3) The training time for HOGA almost linearly decreases with an increase in computing resources. |
| title | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits |
| topic | Machine Learning Hardware Architecture |
| url | https://arxiv.org/abs/2403.01317 |