Efficient FIR filtering with Bit Layer Multiply Accumulator
Fuente:
arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866916145199579136 |
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| author | Liguori, Vincenzo |
| author_facet | Liguori, Vincenzo |
| contents | Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255. After their coefficients were quantized to 16 bits, applying the filter using a BLMAC required, on average, from ~123.3 to ~513.6 additions, depending on the number of taps. A BLMAC dot product machine, specialised for 127 taps FIR filters, was designed for AMD FPGAs. The design footprint is ~110 LUTs, including coefficient and sample storage and is able to apply the filter in ~232 clock cycles on average. This implies a filtering rate of 1.4-3.4 Msamples/s, depending on the FPGA family. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_01351 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Efficient FIR filtering with Bit Layer Multiply Accumulator Liguori, Vincenzo Hardware Architecture Emerging Technologies Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255. After their coefficients were quantized to 16 bits, applying the filter using a BLMAC required, on average, from ~123.3 to ~513.6 additions, depending on the number of taps. A BLMAC dot product machine, specialised for 127 taps FIR filters, was designed for AMD FPGAs. The design footprint is ~110 LUTs, including coefficient and sample storage and is able to apply the filter in ~232 clock cycles on average. This implies a filtering rate of 1.4-3.4 Msamples/s, depending on the FPGA family. |
| title | Efficient FIR filtering with Bit Layer Multiply Accumulator |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2403.01351 |