APA (7th ed.) Citation

Vadde, V., Muralidharan, B., & Sharma, A. (2024). Domain wall and Magnetic Tunnel Junction Hybrid for on-chip Learning in UNet architecture.

Chicago Style (17th ed.) Citation

Vadde, Venkatesh, Bhaskaran Muralidharan, and Abhishek Sharma. Domain Wall and Magnetic Tunnel Junction Hybrid for On-chip Learning in UNet Architecture. 2024.

MLA (9th ed.) Citation

Vadde, Venkatesh, et al. Domain Wall and Magnetic Tunnel Junction Hybrid for On-chip Learning in UNet Architecture. 2024.