Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators

Fuente: arXiv
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Auteurs principaux: Sunny, Febin, Taheri, Ebadollah, Nikdast, Mahdi, Pasricha, Sudeep
Format: Preprint
Publié: 2024
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author Sunny, Febin
Taheri, Ebadollah
Nikdast, Mahdi
Pasricha, Sudeep
author_facet Sunny, Febin
Taheri, Ebadollah
Nikdast, Mahdi
Pasricha, Sudeep
contents Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.
format Preprint
id arxiv_https___arxiv_org_abs_2403_04189
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
Sunny, Febin
Taheri, Ebadollah
Nikdast, Mahdi
Pasricha, Sudeep
Hardware Architecture
Machine Learning
Signal Processing
Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.
title Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
topic Hardware Architecture
Machine Learning
Signal Processing
url https://arxiv.org/abs/2403.04189