Parendi: Thousand-Way Parallel RTL Simulation
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arXiv
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| Autores principales: | , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| Acceso en línea: | |
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| _version_ | 1866913736680275968 |
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| author | Emami, Mahyar Bourgeat, Thomas Larus, James |
| author_facet | Emami, Mahyar Bourgeat, Thomas Larus, James |
| contents | Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance.
Parendi is an RTL simulator that addresses this challenge by exploiting the abundant fine-grained parallelism inherent in RTL simulation and efficiently mapping it onto the massively parallel Graphcore IPU (Intelligence Processing Unit) architecture. Parendi scales up to 5888 cores on 4 Graphcore IPU sockets. It allows us to run large RTL designs up to 4$\times$ faster than the most powerful state-of-the-art x64 multicore systems.
To achieve this performance, we developed new partitioning and compilation techniques and carefully quantified the synchronization, communication, and computation costs of parallel RTL simulation: The paper comprehensively analyzes these factors and details the strategies that Parendi uses to optimize them. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_04714 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Parendi: Thousand-Way Parallel RTL Simulation Emami, Mahyar Bourgeat, Thomas Larus, James Distributed, Parallel, and Cluster Computing Hardware Architecture Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses this challenge by exploiting the abundant fine-grained parallelism inherent in RTL simulation and efficiently mapping it onto the massively parallel Graphcore IPU (Intelligence Processing Unit) architecture. Parendi scales up to 5888 cores on 4 Graphcore IPU sockets. It allows us to run large RTL designs up to 4$\times$ faster than the most powerful state-of-the-art x64 multicore systems. To achieve this performance, we developed new partitioning and compilation techniques and carefully quantified the synchronization, communication, and computation costs of parallel RTL simulation: The paper comprehensively analyzes these factors and details the strategies that Parendi uses to optimize them. |
| title | Parendi: Thousand-Way Parallel RTL Simulation |
| topic | Distributed, Parallel, and Cluster Computing Hardware Architecture |
| url | https://arxiv.org/abs/2403.04714 |