Learning-driven Physically-aware Large-scale Circuit Gate Sizing
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866913263326855168 |
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| author | Ye, Yuyang Xu, Peng Ren, Lizheng Chen, Tinghuan Yan, Hao Yu, Bei Shi, Longxing |
| author_facet | Ye, Yuyang Xu, Peng Ren, Lizheng Chen, Tinghuan Yan, Hao Yu, Bei Shi, Longxing |
| contents | Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_08193 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Learning-driven Physically-aware Large-scale Circuit Gate Sizing Ye, Yuyang Xu, Peng Ren, Lizheng Chen, Tinghuan Yan, Hao Yu, Bei Shi, Longxing Machine Learning Hardware Architecture Emerging Technologies Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool. |
| title | Learning-driven Physically-aware Large-scale Circuit Gate Sizing |
| topic | Machine Learning Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2403.08193 |