Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications
Fuente:
arXiv
Saved in:
| Main Authors: | Weng, Olivia, Redding, Alexander, Tran, Nhan, Duarte, Javier Mauricio, Kastner, Ryan |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Design Rules for Extreme-Edge Scientific Computing on AI Engines
by: Ma, Zhenghua, et al.
Published: (2026)
by: Ma, Zhenghua, et al.
Published: (2026)
A System Architecture for Low Latency Multiprogramming Quantum Computing
by: Zhao, Yilun, et al.
Published: (2026)
by: Zhao, Yilun, et al.
Published: (2026)
Topkima-Former: Low-energy, Low-Latency Inference for Transformers using top-k In-memory ADC
by: Dong, Shuai, et al.
Published: (2024)
by: Dong, Shuai, et al.
Published: (2024)
LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
by: Moon, Seungjae, et al.
Published: (2024)
by: Moon, Seungjae, et al.
Published: (2024)
A Low-Latency FFT-IFFT Cascade Architecture
by: Parhi, Keshab K.
Published: (2023)
by: Parhi, Keshab K.
Published: (2023)
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
by: Que, Zhiqiang, et al.
Published: (2022)
by: Que, Zhiqiang, et al.
Published: (2022)
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
by: Yahya, Jawad Haj, et al.
Published: (2022)
by: Yahya, Jawad Haj, et al.
Published: (2022)
XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
by: Yu, Feng, et al.
Published: (2026)
by: Yu, Feng, et al.
Published: (2026)
A Case for Kolmogorov-Arnold Networks in Prefetching: Towards Low-Latency, Generalizable ML-Based Prefetchers
by: Kulkarni, Dhruv, et al.
Published: (2025)
by: Kulkarni, Dhruv, et al.
Published: (2025)
FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators
by: Abarajithan, G, et al.
Published: (2026)
by: Abarajithan, G, et al.
Published: (2026)
A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network
by: Jiang, Aojie, et al.
Published: (2026)
by: Jiang, Aojie, et al.
Published: (2026)
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator
by: Lin, Kuan-Ting, et al.
Published: (2025)
by: Lin, Kuan-Ting, et al.
Published: (2025)
Data-Rate-Aware High-Speed CNN Inference on FPGAs
by: Habermann, Tobias, et al.
Published: (2026)
by: Habermann, Tobias, et al.
Published: (2026)
Low Power Approximate Multiplier Architecture for Deep Neural Networks
by: Jaswal, Pragun, et al.
Published: (2025)
by: Jaswal, Pragun, et al.
Published: (2025)
TOP: Towards Open & Predictable Heterogeneous SoCs
by: Valente, Luca, et al.
Published: (2024)
by: Valente, Luca, et al.
Published: (2024)
NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions
by: Fayyazi, Arash, et al.
Published: (2023)
by: Fayyazi, Arash, et al.
Published: (2023)
A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks
by: Yi, Zhiqiang, et al.
Published: (2025)
by: Yi, Zhiqiang, et al.
Published: (2025)
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
by: Andronic, Marta, et al.
Published: (2023)
by: Andronic, Marta, et al.
Published: (2023)
ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
by: Manca, Federico, et al.
Published: (2024)
by: Manca, Federico, et al.
Published: (2024)
Evaluation of GPU Video Encoder for Low-Latency Real-Time 4K UHD Encoding
by: Arunruangsirilert, Kasidis, et al.
Published: (2025)
by: Arunruangsirilert, Kasidis, et al.
Published: (2025)
Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
by: Lou, Binglei, et al.
Published: (2026)
by: Lou, Binglei, et al.
Published: (2026)
Low-Latency FPGA Control System for Real-Time Neural Network Processing in CCD-Based Trapped-Ion Qubit Measurement
by: Lou, Binglei, et al.
Published: (2025)
by: Lou, Binglei, et al.
Published: (2025)
Architectural Classification of XR Workloads: Cross-Layer Archetypes and Implications
by: Shi, Xinyu, et al.
Published: (2026)
by: Shi, Xinyu, et al.
Published: (2026)
Configurable Multi-Port Memory Architecture for High-Speed Data Communication
by: Dhakad, Narendra Singh, et al.
Published: (2024)
by: Dhakad, Narendra Singh, et al.
Published: (2024)
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic
by: Gerlinghoff, Daniel, et al.
Published: (2024)
by: Gerlinghoff, Daniel, et al.
Published: (2024)
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture
by: Li, Tenglong, et al.
Published: (2024)
by: Li, Tenglong, et al.
Published: (2024)
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the Edge
by: Tian, Chunlin, et al.
Published: (2025)
by: Tian, Chunlin, et al.
Published: (2025)
System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)
by: Liao, Yuchao, et al.
Published: (2024)
Efficient Sparse Processing-in-Memory Architecture (ESPIM) for Machine Learning Inference
by: He, Mingxuan, et al.
Published: (2024)
by: He, Mingxuan, et al.
Published: (2024)
LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference
by: Zheng, Jianing, et al.
Published: (2025)
by: Zheng, Jianing, et al.
Published: (2025)
LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
by: Ye, Bochen, et al.
Published: (2025)
by: Ye, Bochen, et al.
Published: (2025)
Reconfigurable Stream Network Architecture
by: Wang, Chengyue, et al.
Published: (2024)
by: Wang, Chengyue, et al.
Published: (2024)
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
by: Manoni, Simone, et al.
Published: (2025)
by: Manoni, Simone, et al.
Published: (2025)
Low Latency GNN Accelerator for Quantum Error Correction
by: Cicero, Alessio, et al.
Published: (2026)
by: Cicero, Alessio, et al.
Published: (2026)
FusionCIM: Accelerating LLM Inference with Fusion-Driven Computing-in-Memory Architecture
by: Xuan, Zihao, et al.
Published: (2026)
by: Xuan, Zihao, et al.
Published: (2026)
MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
by: Kirschner, Maximilian, et al.
Published: (2025)
by: Kirschner, Maximilian, et al.
Published: (2025)
Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
by: Kirschner, Maximilian, et al.
Published: (2024)
by: Kirschner, Maximilian, et al.
Published: (2024)
DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP
by: Li, Guoyu, et al.
Published: (2025)
by: Li, Guoyu, et al.
Published: (2025)
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
by: Kumar, Sonu, et al.
Published: (2025)
by: Kumar, Sonu, et al.
Published: (2025)
TENET: An Efficient Sparsity-Aware LUT-Centric Architecture for Ternary LLM Inference On Edge
by: Huang, Zhirui, et al.
Published: (2025)
by: Huang, Zhirui, et al.
Published: (2025)
Similar Items
-
Design Rules for Extreme-Edge Scientific Computing on AI Engines
by: Ma, Zhenghua, et al.
Published: (2026) -
A System Architecture for Low Latency Multiprogramming Quantum Computing
by: Zhao, Yilun, et al.
Published: (2026) -
Topkima-Former: Low-energy, Low-Latency Inference for Transformers using top-k In-memory ADC
by: Dong, Shuai, et al.
Published: (2024) -
LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
by: Moon, Seungjae, et al.
Published: (2024) -
A Low-Latency FFT-IFFT Cascade Architecture
by: Parhi, Keshab K.
Published: (2023)