MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications
Fuente:
arXiv
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| Main Authors: | Rahman, Tousif, Mao, Gang, Maheshwari, Sidharth, Shafik, Rishad, Yakovlev, Alex |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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