AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866916161147371520 |
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| author | Ahmed, Md Rubel Koike-Akino, Toshiaki Parsons, Kieran Wang, Ye |
| author_facet | Ahmed, Md Rubel Koike-Akino, Toshiaki Parsons, Kieran Wang, Ye |
| contents | High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space parameters can take much time and effort for hardware engineers to meet specific design specifications. This paper proposes a novel framework called AutoHLS, which integrates a deep neural network (DNN) with Bayesian optimization (BO) to accelerate HLS hardware design optimization. Our tool focuses on HLS pragma exploration and operation transformation. It utilizes integrated DNNs to predict synthesizability within a given FPGA resource budget. We also investigate the potential of emerging quantum neural networks (QNNs) instead of classical DNNs for the AutoHLS pipeline. Our experimental results demonstrate up to a 70-fold speedup in exploration time. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_10686 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs Ahmed, Md Rubel Koike-Akino, Toshiaki Parsons, Kieran Wang, Ye Hardware Architecture Artificial Intelligence Machine Learning High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space parameters can take much time and effort for hardware engineers to meet specific design specifications. This paper proposes a novel framework called AutoHLS, which integrates a deep neural network (DNN) with Bayesian optimization (BO) to accelerate HLS hardware design optimization. Our tool focuses on HLS pragma exploration and operation transformation. It utilizes integrated DNNs to predict synthesizability within a given FPGA resource budget. We also investigate the potential of emerging quantum neural networks (QNNs) instead of classical DNNs for the AutoHLS pipeline. Our experimental results demonstrate up to a 70-fold speedup in exploration time. |
| title | AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs |
| topic | Hardware Architecture Artificial Intelligence Machine Learning |
| url | https://arxiv.org/abs/2403.10686 |