Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Fuente:
arXiv
Enregistré dans:
| Auteurs principaux: | , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Publié: |
2024
|
| Sujets: | |
| Accès en ligne: | |
| Tags: |
Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!
|
| _version_ | 1866929415412252672 |
|---|---|
| author | Chang, Kaiyan Wang, Kun Yang, Nan Wang, Ying Jin, Dantong Zhu, Wenlong Chen, Zhirong Li, Cangyuan Yan, Hao Zhou, Yunhao Zhao, Zhuoliang Cheng, Yuan Pan, Yudong Liu, Yiqi Wang, Mengdi Liang, Shengwen Han, Yinhe Li, Huawei Li, Xiaowei |
| author_facet | Chang, Kaiyan Wang, Kun Yang, Nan Wang, Ying Jin, Dantong Zhu, Wenlong Chen, Zhirong Li, Cangyuan Yan, Hao Zhou, Yunhao Zhao, Zhuoliang Cheng, Yuan Pan, Yudong Liu, Yiqi Wang, Mengdi Liang, Shengwen Han, Yinhe Li, Huawei Li, Xiaowei |
| contents | Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design. However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs. Additionally, the absence of a Verilog and Electronic Design Automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers. This paper proposes an automated design-data augmentation framework, which generates high-volume and high-quality natural language aligned with Verilog and EDA scripts. For Verilog generation, it translates Verilog files to an abstract syntax tree and then maps nodes to natural language with a predefined template. For Verilog repair, it uses predefined rules to generate the wrong verilog file and then pairs EDA Tool feedback with the right and wrong verilog file. For EDA Script generation, it uses existing LLM(GPT-3.5) to obtain the description of the Script. To evaluate the effectiveness of our data augmentation method, we finetune Llama2-13B and Llama2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model (ChipGPT-FT) has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_11202 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework Chang, Kaiyan Wang, Kun Yang, Nan Wang, Ying Jin, Dantong Zhu, Wenlong Chen, Zhirong Li, Cangyuan Yan, Hao Zhou, Yunhao Zhao, Zhuoliang Cheng, Yuan Pan, Yudong Liu, Yiqi Wang, Mengdi Liang, Shengwen Han, Yinhe Li, Huawei Li, Xiaowei Hardware Architecture Artificial Intelligence Programming Languages Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design. However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs. Additionally, the absence of a Verilog and Electronic Design Automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers. This paper proposes an automated design-data augmentation framework, which generates high-volume and high-quality natural language aligned with Verilog and EDA scripts. For Verilog generation, it translates Verilog files to an abstract syntax tree and then maps nodes to natural language with a predefined template. For Verilog repair, it uses predefined rules to generate the wrong verilog file and then pairs EDA Tool feedback with the right and wrong verilog file. For EDA Script generation, it uses existing LLM(GPT-3.5) to obtain the description of the Script. To evaluate the effectiveness of our data augmentation method, we finetune Llama2-13B and Llama2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model (ChipGPT-FT) has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data. |
| title | Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework |
| topic | Hardware Architecture Artificial Intelligence Programming Languages |
| url | https://arxiv.org/abs/2403.11202 |