Cover Image

Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Gerlinghoff, Daniel, Choong, Benjamin Chen Ming, Goh, Rick Siow Mong, Wong, Weng-Fai, Luo, Tao
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration
by: Yin, Mengyuan, et al.
Published: (2025)

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
by: Yu, Feng, et al.
Published: (2026)

LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators
by: Li, Changhong, et al.
Published: (2025)

SAIL: SRAM-Accelerated LLM Inference System with Lookup-Table-based GEMV
by: Zhang, Jingyao, et al.
Published: (2025)

Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
by: Geens, Robin, et al.
Published: (2026)

SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks
by: Lou, Binglei, et al.
Published: (2025)

T-MAN: Enabling End-to-End Low-Bit LLM Inference on NPUs via Unified Table Lookup
by: Wei, Jianyu, et al.
Published: (2025)

FPPS: An FPGA-Based Point Cloud Processing System
by: Zhou, Xiaofeng, et al.
Published: (2026)

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
by: Fu, Zizhuo, et al.
Published: (2026)

Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization
by: Liebster, Milo, et al.
Published: (2026)

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
by: Petropoulos, Anastasios, et al.
Published: (2025)

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
by: Tagata, Hiroto, et al.
Published: (2025)

Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units
by: Ghaderi, Maedeh, et al.
Published: (2024)

RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
by: Tan, Hongshi, et al.
Published: (2026)

Binary Neural Network Implementation for Handwritten Digit Recognition on FPGA
by: Ertörer, Emir Devlet, et al.
Published: (2025)

A Statically and Dynamically Scalable Soft GPGPU
by: Langhammer, Martin, et al.
Published: (2024)

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)

Embedded FPGA Acceleration of Brain-Like Neural Networks: Online Learning to Scalable Inference
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2025)

Energy-Efficient FPGA Framework for Non-Quantized Convolutional Neural Networks
by: Athanasiadis, Angelos, et al.
Published: (2025)

BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
by: Han, Xiaomeng, et al.
Published: (2025)

Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation
by: Zou, Qingyun, et al.
Published: (2026)

FPGA Resource-aware Structured Pruning for Real-Time Neural Networks
by: Ramhorst, Benjamin, et al.
Published: (2023)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
by: Zhang, Xinmiao, et al.
Published: (2024)

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks
by: Leon, Vasileios, et al.
Published: (2025)

A Scalable FPGA Architecture for Quantum Computing Simulation
by: Belfore II, Lee A.
Published: (2024)

A Scalable Resource Management Layer for FPGA SoCs in 6G Radio Units
by: Bartzoudis, Nikolaos, et al.
Published: (2025)

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
by: Umuroglu, Yaman, et al.
Published: (2025)

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
by: M, Amogh K, et al.
Published: (2025)

A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
by: Gao, Yizhao, et al.
Published: (2024)

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
by: Chen, Chen, et al.
Published: (2025)

Real-Time Adaptive Neural Network on FPGA: Enhancing Adaptability through Dynamic Classifier Selection
by: Bouazzaoui, Achraf El, et al.
Published: (2023)

FireFly-P: FPGA-Accelerated Spiking Neural Network Plasticity for Robust Adaptive Control
by: Li, Tenglong, et al.
Published: (2026)

Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator
by: Wang, Peipei, et al.
Published: (2025)

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
by: Di, Zhixiong, et al.
Published: (2023)

Holistic Optimization Framework for FPGA Accelerators
by: Pouget, Stéphane, et al.
Published: (2025)

KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA
by: Guo, Xiaorang, et al.
Published: (2025)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
by: Zuo, Dongsheng, et al.
Published: (2024)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference
by: Nair, Harideep, et al.
Published: (2024)

A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
by: Ali, Sami Ben, et al.
Published: (2024)