HDLdebugger: Streamlining HDL debugging with Large Language Models
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arXiv
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| Format: | Preprint |
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2024
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| _version_ | 1866916163968040960 |
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| author | Yao, Xufeng Li, Haoyang Chan, Tsz Ho Xiao, Wenyi Yuan, Mingxuan Huang, Yu Chen, Lei Yu, Bei |
| author_facet | Yao, Xufeng Li, Haoyang Chan, Tsz Ho Xiao, Wenyi Yuan, Mingxuan Huang, Yu Chen, Lei Yu, Bei |
| contents | In the domain of chip design, Hardware Description Languages (HDLs) play a pivotal role. However, due to the complex syntax of HDLs and the limited availability of online resources, debugging HDL codes remains a difficult and time-intensive task, even for seasoned engineers. Consequently, there is a pressing need to develop automated HDL code debugging models, which can alleviate the burden on hardware engineers. Despite the strong capabilities of Large Language Models (LLMs) in generating, completing, and debugging software code, their utilization in the specialized field of HDL debugging has been limited and, to date, has not yielded satisfactory results. In this paper, we propose an LLM-assisted HDL debugging framework, namely HDLdebugger, which consists of HDL debugging data generation via a reverse engineering approach, a search engine for retrieval-augmented generation, and a retrieval-augmented LLM fine-tuning approach. Through the integration of these components, HDLdebugger can automate and streamline HDL debugging for chip design. Our comprehensive experiments, conducted on an HDL code dataset sourced from Huawei, reveal that HDLdebugger outperforms 13 cutting-edge LLM baselines, displaying exceptional effectiveness in HDL code debugging. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_11671 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | HDLdebugger: Streamlining HDL debugging with Large Language Models Yao, Xufeng Li, Haoyang Chan, Tsz Ho Xiao, Wenyi Yuan, Mingxuan Huang, Yu Chen, Lei Yu, Bei Hardware Architecture Artificial Intelligence Computational Engineering, Finance, and Science Machine Learning Software Engineering In the domain of chip design, Hardware Description Languages (HDLs) play a pivotal role. However, due to the complex syntax of HDLs and the limited availability of online resources, debugging HDL codes remains a difficult and time-intensive task, even for seasoned engineers. Consequently, there is a pressing need to develop automated HDL code debugging models, which can alleviate the burden on hardware engineers. Despite the strong capabilities of Large Language Models (LLMs) in generating, completing, and debugging software code, their utilization in the specialized field of HDL debugging has been limited and, to date, has not yielded satisfactory results. In this paper, we propose an LLM-assisted HDL debugging framework, namely HDLdebugger, which consists of HDL debugging data generation via a reverse engineering approach, a search engine for retrieval-augmented generation, and a retrieval-augmented LLM fine-tuning approach. Through the integration of these components, HDLdebugger can automate and streamline HDL debugging for chip design. Our comprehensive experiments, conducted on an HDL code dataset sourced from Huawei, reveal that HDLdebugger outperforms 13 cutting-edge LLM baselines, displaying exceptional effectiveness in HDL code debugging. |
| title | HDLdebugger: Streamlining HDL debugging with Large Language Models |
| topic | Hardware Architecture Artificial Intelligence Computational Engineering, Finance, and Science Machine Learning Software Engineering |
| url | https://arxiv.org/abs/2403.11671 |