Cover Image

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Chen, Chen, Hu, Guangyu, Zuo, Dongsheng, Yu, Cunxi, Ma, Yuzhe, Zhang, Hongce
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Programming Languages
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
by: Chen, Chen, et al.
Published: (2025)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)

HEC: Equivalence Verification Checking for Code Transformation via Equality Saturation
by: Yin, Jiaqi, et al.
Published: (2025)

AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
by: Hu, Guangyu, et al.
Published: (2026)

BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning
by: Miao, Mingkai, et al.
Published: (2025)

Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)

Revisit Choice Network for Synthesis and Technology Mapping
by: Chen, Chen, et al.
Published: (2025)

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
by: Yu, Cunxi
Published: (2025)

Scaling Program Synthesis Based Technology Mapping with Equality Saturation
by: Smith, Gus Henry, et al.
Published: (2024)

FPGA Technology Mapping Using Sketch-Guided Program Synthesis
by: Smith, Gus Henry, et al.
Published: (2024)

Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
by: Xu, Haocheng, et al.
Published: (2024)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
by: Zuo, Dongsheng, et al.
Published: (2024)

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
by: ouyang, Yikang, et al.
Published: (2026)

BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
by: Yin, Jiaqi, et al.
Published: (2025)

An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
by: Zhang, Weichuang, et al.
Published: (2024)

EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning
by: Hu, Guangyu, et al.
Published: (2026)

LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

The Program Hypergraph: Multi-Way Relational Structure for Geometric Algebra, Spatial Compute, and Physics-Aware Compilation
by: Haynes, Houston
Published: (2026)

AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
by: Tan, Yan, et al.
Published: (2026)

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
by: Zhang, Yang, et al.
Published: (2025)

e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
by: Yin, Jiaqi, et al.
Published: (2025)

VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
by: Zhao, Jiayu, et al.
Published: (2025)

PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization
by: Zuo, Dongsheng, et al.
Published: (2025)

RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction
by: Zuo, Dongsheng, et al.
Published: (2024)

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
by: Zhuang, Jinming, et al.
Published: (2024)

SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
by: Chang, Fu-Chieh, et al.
Published: (2026)

Partial Cross-Compilation and Mixed Execution for Accelerating Dynamic Binary Translation
by: Gu, Yuhao, et al.
Published: (2025)

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
by: Zhao, Zhuorui, et al.
Published: (2025)

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
by: Yang, Yiyao, et al.
Published: (2025)

NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
by: Li, Shangkun, et al.
Published: (2026)

ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)

Aligning Netlist to Source Code using SynAlign
by: Garg, Sakshi, et al.
Published: (2025)

DAG-aware Synthesis Orchestration
by: Li, Yingjie, et al.
Published: (2023)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
by: Xu, Siyi, et al.
Published: (2025)

Register Aggregation for Hardware Decompilation
by: Rao, Varun, et al.
Published: (2024)

Relaxed exception semantics for Arm-A (extended version)
by: Simner, Ben, et al.
Published: (2024)

WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissions
by: Lin, Zhengyao, et al.
Published: (2023)

There and Back Again: A Netlist's Tale with Much Egraphin'
by: Smith, Gus Henry, et al.
Published: (2024)