NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
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arXiv
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| Main Authors: | , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866929496764973056 |
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| author | Zhou, Zhe Chen, Yiqi Zhang, Tao Wang, Yang Shu, Ran Xu, Shuotao Cheng, Peng Qu, Lei Xiong, Yongqiang Zhang, Jie Sun, Guangyu |
| author_facet | Zhou, Zhe Chen, Yiqi Zhang, Tao Wang, Yang Shu, Ran Xu, Shuotao Cheng, Peng Qu, Lei Xiong, Yongqiang Zhang, Jie Sun, Guangyu |
| contents | The Compute Express Link (CXL) interconnect makes it feasible to integrate diverse types of memory into servers via its byte-addressable SerDes links. Considering the various access latency, harnessing the full potential of CXL-based heterogeneous memory systems requires efficient memory tiering. However, prior work can hardly make a fundamental progress owing to low-resolution and high-overhead memory access profiling techniques. To address this critical challenge, we propose a novel memory tiering solution called NeoMem, which features a hardware/software co-design. NeoMem offloads memory profiling functions to CXL device-side controllers, integrating a dedicated hardware unit called NeoProf. NeoProf readily monitors memory accesses and provides the OS with crucial page hotness statistics and other useful system state information. On the OS kernel side, we design a revamped memory-tiering strategy, enabling accurate and timely hot page promotion based on NeoProf statistics. We implement NeoMem on a real FPGA-based CXL memory platform and Linux kernel v6.3. Comprehensive evaluations demonstrate that NeoMem achieves 32% to 67% geomean speedup over several existing memory tiering solutions. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_18702 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering Zhou, Zhe Chen, Yiqi Zhang, Tao Wang, Yang Shu, Ran Xu, Shuotao Cheng, Peng Qu, Lei Xiong, Yongqiang Zhang, Jie Sun, Guangyu Hardware Architecture The Compute Express Link (CXL) interconnect makes it feasible to integrate diverse types of memory into servers via its byte-addressable SerDes links. Considering the various access latency, harnessing the full potential of CXL-based heterogeneous memory systems requires efficient memory tiering. However, prior work can hardly make a fundamental progress owing to low-resolution and high-overhead memory access profiling techniques. To address this critical challenge, we propose a novel memory tiering solution called NeoMem, which features a hardware/software co-design. NeoMem offloads memory profiling functions to CXL device-side controllers, integrating a dedicated hardware unit called NeoProf. NeoProf readily monitors memory accesses and provides the OS with crucial page hotness statistics and other useful system state information. On the OS kernel side, we design a revamped memory-tiering strategy, enabling accurate and timely hot page promotion based on NeoProf statistics. We implement NeoMem on a real FPGA-based CXL memory platform and Linux kernel v6.3. Comprehensive evaluations demonstrate that NeoMem achieves 32% to 67% geomean speedup over several existing memory tiering solutions. |
| title | NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2403.18702 |