Testing Resource Isolation for System-on-Chip Architectures

Fuente: arXiv
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Main Authors: Ledent, Philippe, Mateescu, Radu, Serwe, Wendelin
Format: Preprint
Published: 2024
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author Ledent, Philippe
Mateescu, Radu
Serwe, Wendelin
author_facet Ledent, Philippe
Mateescu, Radu
Serwe, Wendelin
contents Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.
format Preprint
id arxiv_https___arxiv_org_abs_2403_18720
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Testing Resource Isolation for System-on-Chip Architectures
Ledent, Philippe
Mateescu, Radu
Serwe, Wendelin
Hardware Architecture
Cryptography and Security
Software Engineering
Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.
title Testing Resource Isolation for System-on-Chip Architectures
topic Hardware Architecture
Cryptography and Security
Software Engineering
url https://arxiv.org/abs/2403.18720