Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
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| Autores principales: | , , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866910388494270464 |
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| author | Sharma, Harsh Narang, Gaurav Doppa, Janardhan Rao Ogras, Umit Pande, Partha Pratim |
| author_facet | Sharma, Harsh Narang, Gaurav Doppa, Janardhan Rao Ogras, Umit Pande, Partha Pratim |
| contents | Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient and high-performance acceleration of deep learning (DL) workloads. Resistive random-access memory (ReRAM) is one of the most promising technologies to implement PIM. However, as the complexity of Deep convolutional neural networks (DNNs) grows, we need to design a manycore architecture with multiple ReRAM-based processing elements (PEs) on a single chip. Existing PIM-based architectures mostly focus on computation while ignoring the role of communication. ReRAM-based tiled manycore architectures often involve many Processing Elements (PEs), which need to be interconnected via an efficient on-chip communication infrastructure. Simply allocating more resources (ReRAMs) to speed up only computation is ineffective if the communication infrastructure cannot keep up with it. In this paper, we highlight the design principles of a dataflow-aware PIM-enabled manycore platform tailor-made for various types of DL workloads. We consider the design challenges with both 2.5D interposer- and 3D integration-enabled architectures. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2403_19073 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads Sharma, Harsh Narang, Gaurav Doppa, Janardhan Rao Ogras, Umit Pande, Partha Pratim Hardware Architecture Artificial Intelligence Emerging Technologies Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient and high-performance acceleration of deep learning (DL) workloads. Resistive random-access memory (ReRAM) is one of the most promising technologies to implement PIM. However, as the complexity of Deep convolutional neural networks (DNNs) grows, we need to design a manycore architecture with multiple ReRAM-based processing elements (PEs) on a single chip. Existing PIM-based architectures mostly focus on computation while ignoring the role of communication. ReRAM-based tiled manycore architectures often involve many Processing Elements (PEs), which need to be interconnected via an efficient on-chip communication infrastructure. Simply allocating more resources (ReRAMs) to speed up only computation is ineffective if the communication infrastructure cannot keep up with it. In this paper, we highlight the design principles of a dataflow-aware PIM-enabled manycore platform tailor-made for various types of DL workloads. We consider the design challenges with both 2.5D interposer- and 3D integration-enabled architectures. |
| title | Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads |
| topic | Hardware Architecture Artificial Intelligence Emerging Technologies |
| url | https://arxiv.org/abs/2403.19073 |