Saved in:
| Main Authors: | Wang, Runxi, Han, Jun-Han, Stan, Mircea, Guo, Xinfei |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2403.20050 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs
by: Wang, Runxi, et al.
Published: (2025)
by: Wang, Runxi, et al.
Published: (2025)
Shift-Left Techniques in Electronic Design Automation: A Survey
by: Wu, Xinyue, et al.
Published: (2025)
by: Wu, Xinyue, et al.
Published: (2025)
WISP: Image Segmentation-Based Whitespace Diagnosis for Optimal Rectilinear Floorplanning
by: Zhao, Xiaotian, et al.
Published: (2025)
by: Zhao, Xiaotian, et al.
Published: (2025)
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
by: Emami, Mahyar, et al.
Published: (2023)
by: Emami, Mahyar, et al.
Published: (2023)
DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness
by: Zhao, Xiaotian, et al.
Published: (2025)
by: Zhao, Xiaotian, et al.
Published: (2025)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)
by: Yin, Shuo, et al.
Published: (2026)
LEGO: Spatial Accelerator Generation and Optimization for Tensor Applications
by: Lin, Yujun, et al.
Published: (2025)
by: Lin, Yujun, et al.
Published: (2025)
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)
by: Chao, Zhiteng, et al.
Published: (2025)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)
by: Fang, Wenji, et al.
Published: (2026)
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
by: Wu, Fenghua, et al.
Published: (2025)
by: Wu, Fenghua, et al.
Published: (2025)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)
by: Zhu, Yan, et al.
Published: (2026)
by: Zhu, Yan, et al.
Published: (2026)
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)
by: Qin, Kun, et al.
Published: (2025)
UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)
by: Hu, Yuchen, et al.
Published: (2024)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)
by: Li, Chengxi, et al.
Published: (2025)
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
by: Sarkar, Rishov, et al.
Published: (2025)
by: Sarkar, Rishov, et al.
Published: (2025)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)
by: Deng, Chenhui, et al.
Published: (2026)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)
by: Coward, Samuel, et al.
Published: (2024)
Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
by: Sehm, Robin, et al.
Published: (2025)
by: Sehm, Robin, et al.
Published: (2025)
Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits
by: Babu, Shaik Jani, et al.
Published: (2025)
by: Babu, Shaik Jani, et al.
Published: (2025)
Parendi: Thousand-Way Parallel RTL Simulation
by: Emami, Mahyar, et al.
Published: (2024)
by: Emami, Mahyar, et al.
Published: (2024)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)
by: Allam, Ahmed, et al.
Published: (2024)
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)
by: Tsai, Yun-Da, et al.
Published: (2023)
Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)
by: Ifrim, Rares, et al.
Published: (2025)
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
by: Cai, Siyang, et al.
Published: (2026)
by: Cai, Siyang, et al.
Published: (2026)
MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
by: Chaurasia, Ansh
Published: (2025)
by: Chaurasia, Ansh
Published: (2025)
VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)
by: Qi, Haomin, et al.
Published: (2025)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)
by: Deng, Chenhui, et al.
Published: (2025)
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025)
by: Zhou, Jie, et al.
Published: (2025)
From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
by: Wang, Yonghao, et al.
Published: (2026)
by: Wang, Yonghao, et al.
Published: (2026)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
by: Zoni, Davide, et al.
Published: (2025)
by: Zoni, Davide, et al.
Published: (2025)
RTL++: Graph-enhanced LLM for RTL Code Generation
by: Akyash, Mohammad, et al.
Published: (2025)
by: Akyash, Mohammad, et al.
Published: (2025)
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators
by: Wang, Xinyu, et al.
Published: (2024)
by: Wang, Xinyu, et al.
Published: (2024)
Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators
by: Wu, Junchi, et al.
Published: (2025)
by: Wu, Junchi, et al.
Published: (2025)
Similar Items
-
Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs
by: Wang, Runxi, et al.
Published: (2025) -
Shift-Left Techniques in Electronic Design Automation: A Survey
by: Wu, Xinyue, et al.
Published: (2025) -
WISP: Image Segmentation-Based Whitespace Diagnosis for Optimal Rectilinear Floorplanning
by: Zhao, Xiaotian, et al.
Published: (2025) -
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025) -
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)