Memory Sharing with CXL: Hardware and Software Design Approaches
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866910398362419200 |
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| author | Jain, Sunita Yeleswarapu, Nagaradhesh Maruf, Hasan Al Gupta, Rita |
| author_facet | Jain, Sunita Yeleswarapu, Nagaradhesh Maruf, Hasan Al Gupta, Rita |
| contents | Compute Express Link (CXL) is a rapidly emerging coherent interconnect standard that provides opportunities for memory pooling and sharing. Memory sharing is a well-established software feature that improves memory utilization by avoiding unnecessary data movement. In this paper, we discuss multiple approaches to enable memory sharing with different generations of CXL protocol (i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the architectures from the device hardware and software viewpoint. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2404_03245 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Memory Sharing with CXL: Hardware and Software Design Approaches Jain, Sunita Yeleswarapu, Nagaradhesh Maruf, Hasan Al Gupta, Rita Emerging Technologies Operating Systems Compute Express Link (CXL) is a rapidly emerging coherent interconnect standard that provides opportunities for memory pooling and sharing. Memory sharing is a well-established software feature that improves memory utilization by avoiding unnecessary data movement. In this paper, we discuss multiple approaches to enable memory sharing with different generations of CXL protocol (i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the architectures from the device hardware and software viewpoint. |
| title | Memory Sharing with CXL: Hardware and Software Design Approaches |
| topic | Emerging Technologies Operating Systems |
| url | https://arxiv.org/abs/2404.03245 |