Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design
Fuente:
arXiv
Salvato in:
| Autori principali: | , , , , |
|---|---|
| Natura: | Preprint |
| Pubblicazione: |
2024
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1866914795405443072 |
|---|---|
| author | Andrulis, Tanner Chen, Ruicong Lee, Hae-Seung Emer, Joel S. Sze, Vivienne |
| author_facet | Andrulis, Tanner Chen, Ruicong Lee, Hae-Seung Emer, Joel S. Sze, Vivienne |
| contents | Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so architecture-level ADC decisions such as ADC resolution or number of ADCs can significantly impact overall CiM accelerator energy and area. Therefore, modeling how architecture-level decisions affect ADC energy and area is critical for performing architecture-level design space exploration of CiM accelerators.
This work presents an open-source architecture-level model to estimate ADC energy and area. To enable fast design space exploration, the model uses only architecture-level attributes while abstracting circuit-level details. Our model enables researchers to quickly and easily model key architecture-level tradeoffs in accelerators that use ADCs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2404_06553 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design Andrulis, Tanner Chen, Ruicong Lee, Hae-Seung Emer, Joel S. Sze, Vivienne Hardware Architecture Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so architecture-level ADC decisions such as ADC resolution or number of ADCs can significantly impact overall CiM accelerator energy and area. Therefore, modeling how architecture-level decisions affect ADC energy and area is critical for performing architecture-level design space exploration of CiM accelerators. This work presents an open-source architecture-level model to estimate ADC energy and area. To enable fast design space exploration, the model uses only architecture-level attributes while abstracting circuit-level details. Our model enables researchers to quickly and easily model key architecture-level tradeoffs in accelerators that use ADCs. |
| title | Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2404.06553 |