Error Detection and Correction Codes for Safe In-Memory Computations
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arXiv
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| Format: | Preprint |
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2024
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| author | Parrini, Luca Soliman, Taha Hettwer, Benjamin Borrmann, Jan Micha Singh, Simranjeet Bende, Ankit Rana, Vikas Merchant, Farhad Wehn, Norbert |
| author_facet | Parrini, Luca Soliman, Taha Hettwer, Benjamin Borrmann, Jan Micha Singh, Simranjeet Bende, Ankit Rana, Vikas Merchant, Farhad Wehn, Norbert |
| contents | In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities and defects of emerging technologies used in advanced IMC can severely degrade the accuracy of inferred Neural Networks (NN) and lead to malfunctions in safety-critical applications. In this paper, we investigate an architectural-level mitigation technique based on the coordinated action of multiple checksum codes, to detect and correct errors at run-time. This implementation demonstrates higher efficiency in recovering accuracy across different AI algorithms and technologies compared to more traditional methods such as Triple Modular Redundancy (TMR). The results show that several configurations of our implementation recover more than 91% of the original accuracy with less than half of the area required by TMR and less than 40% of latency overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2404_09818 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Error Detection and Correction Codes for Safe In-Memory Computations Parrini, Luca Soliman, Taha Hettwer, Benjamin Borrmann, Jan Micha Singh, Simranjeet Bende, Ankit Rana, Vikas Merchant, Farhad Wehn, Norbert Hardware Architecture In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities and defects of emerging technologies used in advanced IMC can severely degrade the accuracy of inferred Neural Networks (NN) and lead to malfunctions in safety-critical applications. In this paper, we investigate an architectural-level mitigation technique based on the coordinated action of multiple checksum codes, to detect and correct errors at run-time. This implementation demonstrates higher efficiency in recovering accuracy across different AI algorithms and technologies compared to more traditional methods such as Triple Modular Redundancy (TMR). The results show that several configurations of our implementation recover more than 91% of the original accuracy with less than half of the area required by TMR and less than 40% of latency overhead. |
| title | Error Detection and Correction Codes for Safe In-Memory Computations |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2404.09818 |