Method for efficient large-scale cryogenic characterization of CMOS technologies
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866918095244754944 |
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| author | Eastoe, Jonathan Noah, Grayson M. Dutta, Debargha Rossi, Alessandro Fletcher, Jonathan D. Gomez-Saiz, Alberto |
| author_facet | Eastoe, Jonathan Noah, Grayson M. Dutta, Debargha Rossi, Alessandro Fletcher, Jonathan D. Gomez-Saiz, Alberto |
| contents | Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient ($\sim$3.5+ K) to allow for analog signal chain components (e.g. amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g. -55 °C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform DC measurements with Kelvin sense of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2404_11451 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Method for efficient large-scale cryogenic characterization of CMOS technologies Eastoe, Jonathan Noah, Grayson M. Dutta, Debargha Rossi, Alessandro Fletcher, Jonathan D. Gomez-Saiz, Alberto Mesoscale and Nanoscale Physics Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient ($\sim$3.5+ K) to allow for analog signal chain components (e.g. amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g. -55 °C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform DC measurements with Kelvin sense of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup. |
| title | Method for efficient large-scale cryogenic characterization of CMOS technologies |
| topic | Mesoscale and Nanoscale Physics |
| url | https://arxiv.org/abs/2404.11451 |