Gespeichert in:
| Hauptverfasser: | , , , , , , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| Schlagworte: | |
| Online-Zugang: | https://arxiv.org/abs/2404.13801 |
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Inhaltsangabe:
- Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors through ab initio quantum transport simulations. Our simulation results demonstrate that, through appropriate doping and dielectric engineering, the sub-1-nm devices can meet the requirement of extended 'ITRS'(International Technology Roadmap for Semiconductors) $L_g$=0.34 nm. Following device optimization, we achieve impressive maximum on-state current densities of 409 $μA / μm$ for n-type and 800 $μA / μm$ for p-type high-performance (HP) devices, while n-type and p-type low-power (LP) devices exhibit maximum on-state current densities of 75 $μA / μm$ and 187 $μA / μm$, respectively. We employed the Wentzel-Kramer-Brillouin (WKB) approximation to explain the physical mechanisms of underlap and spacer region optimization on transistor performance. The underlap and spacer regions primarily influence the transport properties of sub-1-nm transistors by respectively altering the width and body factor of the potential barriers. Compared to ML $MoS_2$ transistors with a 1 nm gate length, our sub-1-nm gate length HP and LP ML $MoS_2$ transistors exhibit lower energy-delay products. Hence the sub-1-nm gate length transistors have immense potential for driving the next generation of electronics.