:: Library Catalog

Imagen de Portada

Guardado en:

Detalles Bibliográficos
Autores principales:	Drane, Theo, Coward, Samuel, Temel, Mertcan, Leslie-Hurd, Joe
Formato:	Preprint
Publicado:	2024
Materias:	Hardware Architecture
Acceso en línea:	https://arxiv.org/abs/2404.14069
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

ROVER: RTL Optimization via Verified E-Graph Rewriting
por: Coward, Samuel, et al.
Publicado: (2024)

Combining Power and Arithmetic Optimization via Datapath Rewriting
por: Coward, Samuel, et al.
Publicado: (2024)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
por: Böttcher, Andreas, et al.
Publicado: (2024)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
por: Zuo, Dongsheng, et al.
Publicado: (2024)

ReducedLUT: Table Decomposition with "Don't Care" Conditions
por: Cassidy, Oliver, et al.
Publicado: (2024)

Efficient Multi-Cycle Folded Integer Multipliers
por: Houraniah, Ahmad, et al.
Publicado: (2023)

An Architectural Error Metric for CNN-Oriented Approximate Multipliers
por: Liu, Ao, et al.
Publicado: (2024)

An Energy-Efficient Approximate Posit Multiply-Divide Unit
por: Thotli, Rishi, et al.
Publicado: (2026)

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators
por: Xue, Chenhao, et al.
Publicado: (2025)

Flexible Bit-Truncation Memory for Approximate Applications on the Edge
por: Oswald, William, et al.
Publicado: (2025)

Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
por: Ifrim, Rares, et al.
Publicado: (2025)

Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines
por: Alexandridis, Kosmas, et al.
Publicado: (2024)

Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations
por: Mohammad, Sakib, et al.
Publicado: (2024)

Hardware-Efficient CNNs: Interleaved Approximate FP32 Multipliers for Kernel Computation
por: Gowda, Bindu G, et al.
Publicado: (2025)

Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs
por: Kida, Misaki, et al.
Publicado: (2025)

HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing
por: Vafaei, Jafar, et al.
Publicado: (2024)

FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
por: Ranjbar, Ali, et al.
Publicado: (2025)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
por: Böttcher, Andreas, et al.
Publicado: (2024)

A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing
por: Chowdhury, Md Rownak Hossain, et al.
Publicado: (2026)

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit
por: Vellaisamy, Prabhu, et al.
Publicado: (2024)

Jack Unit: An Area- and Energy-Efficient Multiply-Accumulate (MAC) Unit Supporting Diverse Data Formats
por: Noh, Seock-Hwan, et al.
Publicado: (2025)

A Novel FPGA-based CNN Hardware Accelerator: Optimization for Convolutional Layers using Karatsuba Ofman Multiplier
por: Sarkar, Amit
Publicado: (2024)

Leveraging Highly Approximated Multipliers in DNN Inference
por: Zervakis, Georgios, et al.
Publicado: (2024)

A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
por: Ali, Sami Ben, et al.
Publicado: (2024)

Efficient FIR filtering with Bit Layer Multiply Accumulator
por: Liguori, Vincenzo
Publicado: (2024)

Implementation of a 8-bit Wallace Tree Multiplier
por: Biswas, Ayan, et al.
Publicado: (2025)

Count2Multiply: Reliable In-Memory High-Radix Counting
por: de Lima, João Paulo Cardoso, et al.
Publicado: (2024)

Approximate Multiplier Induced Error Propagation in Deep Neural Networks
por: Alahakoon, A. M. H. H., et al.
Publicado: (2025)

Low Power Approximate Multiplier Architecture for Deep Neural Networks
por: Jaswal, Pragun, et al.
Publicado: (2025)

Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations
por: Heidary, Masoud, et al.
Publicado: (2026)

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
por: Jaswal, Pragun, et al.
Publicado: (2026)

Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
por: Kumari, Ruby, et al.
Publicado: (2025)

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
por: Sonnino, Lorenzo, et al.
Publicado: (2023)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators
por: Vellaisamy, Prabhu, et al.
Publicado: (2026)

AxMoE: Characterizing the Impact of Approximate Multipliers on Mixture-of-Experts DNN Architectures
por: Shende, Omkar B, et al.
Publicado: (2026)

Generalized Methodology for Determining Numerical Features of Hardware Floating-Point Matrix Multipliers: Part I
por: Khattak, Faizan A, et al.
Publicado: (2025)

RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction
por: Zuo, Dongsheng, et al.
Publicado: (2024)

A Systematic Characterization of LLM Inference on GPUs
por: Wang, Haonan, et al.
Publicado: (2025)

Faithful Dynamic Timing Analysis of Digital Circuits Using Continuous Thresholded Mode-Switched ODEs
por: Ferdowsi, Arman, et al.
Publicado: (2024)

Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers
por: Arnold, Felix, et al.
Publicado: (2025)