TDRAM: Tag-enhanced DRAM for Efficient Caching
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arXiv
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| Autori principali: | , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| author | Babaie, Maryam Akram, Ayaz Elsasser, Wendy Haukness, Brent Miller, Michael Song, Taeksang Vogelsang, Thomas Woo, Steven Lowe-Power, Jason |
| author_facet | Babaie, Maryam Akram, Ayaz Elsasser, Wendy Haukness, Brent Miller, Michael Song, Taeksang Vogelsang, Thomas Woo, Steven Lowe-Power, Jason |
| contents | As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can improve the performance of memory systems, existing DRAM cache designs suffer from high miss penalties, wasted data movement, and interference between misses and demand requests. In this paper, we propose TDRAM, a novel DRAM microarchitecture tailored for caching. TDRAM enhances HBM3 by adding a set of small low-latency mats to store tags and metadata on the same die as the data mats. These mats enable fast parallel tag and data access, on-DRAM-die tag comparison, and conditional data response based on comparison result (reducing wasted data transfers) akin to SRAM caches mechanism. TDRAM further optimizes the hit and miss latencies by performing opportunistic early tag probing. Moreover, TDRAM introduces a flush buffer to store conflicting dirty data on write misses, eliminating turnaround delays on data bus. We evaluate TDRAM using a full-system simulator and a set of HPC workloads with large memory footprints showing TDRAM provides at least 2.6$\times$ faster tag check, 1.2$\times$ speedup, and 21% less energy consumption, compared to the state-of-the-art commercial and research designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2404_14617 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | TDRAM: Tag-enhanced DRAM for Efficient Caching Babaie, Maryam Akram, Ayaz Elsasser, Wendy Haukness, Brent Miller, Michael Song, Taeksang Vogelsang, Thomas Woo, Steven Lowe-Power, Jason Hardware Architecture As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can improve the performance of memory systems, existing DRAM cache designs suffer from high miss penalties, wasted data movement, and interference between misses and demand requests. In this paper, we propose TDRAM, a novel DRAM microarchitecture tailored for caching. TDRAM enhances HBM3 by adding a set of small low-latency mats to store tags and metadata on the same die as the data mats. These mats enable fast parallel tag and data access, on-DRAM-die tag comparison, and conditional data response based on comparison result (reducing wasted data transfers) akin to SRAM caches mechanism. TDRAM further optimizes the hit and miss latencies by performing opportunistic early tag probing. Moreover, TDRAM introduces a flush buffer to store conflicting dirty data on write misses, eliminating turnaround delays on data bus. We evaluate TDRAM using a full-system simulator and a set of HPC workloads with large memory footprints showing TDRAM provides at least 2.6$\times$ faster tag check, 1.2$\times$ speedup, and 21% less energy consumption, compared to the state-of-the-art commercial and research designs. |
| title | TDRAM: Tag-enhanced DRAM for Efficient Caching |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2404.14617 |