A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator

Fuente: arXiv

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Bibliographic Details
Main Authors:	Bause, Oliver, Bernardo, Paul Palomero, Bringmann, Oliver
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2404.15823