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Main Authors: Mayoral-Vilches, Víctor, Reina-Muñoz, Juan Manuel, Crespo-Álvarez, Martiño, Mayoral-Vilches, David
Format: Preprint
Published: 2024
Subjects:
Online Access:https://arxiv.org/abs/2404.18208
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author Mayoral-Vilches, Víctor
Reina-Muñoz, Juan Manuel
Crespo-Álvarez, Martiño
Mayoral-Vilches, David
author_facet Mayoral-Vilches, Víctor
Reina-Muñoz, Juan Manuel
Crespo-Álvarez, Martiño
Mayoral-Vilches, David
contents The Robot Operating System (ROS) pubsub model played a pivotal role in developing sophisticated robotic applications. However, the complexities and real-time demands of modern robotics necessitate more efficient communication solutions that are deterministic and isochronous. This article introduces a groundbreaking approach: embedding ROS 2 message-passing infrastructure directly onto a specialized hardware chip, significantly enhancing speed and efficiency in robotic communications. Our FPGA prototypes of the chip design can send or receive packages in less than 2.5 microseconds, accelerating networking communications by more than 62x on average and improving energy consumption by more than 500x when compared to traditional ROS 2 software implementations on modern CPUs. Additionally, it dramatically reduces maximum latency in ROS 2 networking communication by more than 30,000x. In situations of peak latency, our design guarantees an isochronous response within 11 microseconds, a stark improvement over the potential hundreds of milliseconds reported by modern CPU systems under similar conditions.
format Preprint
id arxiv_https___arxiv_org_abs_2404_18208
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle ROS 2 on a Chip, Achieving Brain-Like Speeds and Efficiency in Robotic Networking
Mayoral-Vilches, Víctor
Reina-Muñoz, Juan Manuel
Crespo-Álvarez, Martiño
Mayoral-Vilches, David
Robotics
The Robot Operating System (ROS) pubsub model played a pivotal role in developing sophisticated robotic applications. However, the complexities and real-time demands of modern robotics necessitate more efficient communication solutions that are deterministic and isochronous. This article introduces a groundbreaking approach: embedding ROS 2 message-passing infrastructure directly onto a specialized hardware chip, significantly enhancing speed and efficiency in robotic communications. Our FPGA prototypes of the chip design can send or receive packages in less than 2.5 microseconds, accelerating networking communications by more than 62x on average and improving energy consumption by more than 500x when compared to traditional ROS 2 software implementations on modern CPUs. Additionally, it dramatically reduces maximum latency in ROS 2 networking communication by more than 30,000x. In situations of peak latency, our design guarantees an isochronous response within 11 microseconds, a stark improvement over the potential hundreds of milliseconds reported by modern CPU systems under similar conditions.
title ROS 2 on a Chip, Achieving Brain-Like Speeds and Efficiency in Robotic Networking
topic Robotics
url https://arxiv.org/abs/2404.18208