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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2404.19246 |
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| _version_ | 1866909185346633728 |
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| author | Calderon, Mateo Jalen Andrew Lucas, Lee Jun Lei Rosli, Syarifuddin Azhar Bin Ying, Stephanie See Hui Yu, Jarell Lim En Xiang, Maoyang Teo, T. Hui |
| author_facet | Calderon, Mateo Jalen Andrew Lucas, Lee Jun Lei Rosli, Syarifuddin Azhar Bin Ying, Stephanie See Hui Yu, Jarell Lim En Xiang, Maoyang Teo, T. Hui |
| contents | This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The system integrates additional FPGA modules for real-time interaction and visualisation, including a clock generator, UART interface, XADC, and a 7-segment display driver. These components facilitate the direct display of PRNG values on the FPGA and the transmission of data to a laptop for histogram analysis, verifying the Gaussian nature of the output. This approach demonstrates the practical application of chaotic systems for generating Gaussian-distributed pseudo-random numbers in digital hardware, highlighting the logistic map's potential in PRNG design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2404_19246 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Logistic Map Pseudo Random Number Generator in FPGA Calderon, Mateo Jalen Andrew Lucas, Lee Jun Lei Rosli, Syarifuddin Azhar Bin Ying, Stephanie See Hui Yu, Jarell Lim En Xiang, Maoyang Teo, T. Hui Cryptography and Security Hardware Architecture This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The system integrates additional FPGA modules for real-time interaction and visualisation, including a clock generator, UART interface, XADC, and a 7-segment display driver. These components facilitate the direct display of PRNG values on the FPGA and the transmission of data to a laptop for histogram analysis, verifying the Gaussian nature of the output. This approach demonstrates the practical application of chaotic systems for generating Gaussian-distributed pseudo-random numbers in digital hardware, highlighting the logistic map's potential in PRNG design. |
| title | Logistic Map Pseudo Random Number Generator in FPGA |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2404.19246 |