PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914849401864192 |
|---|---|
| author | Ribeiro, Lucas Grativol Gauthier, Lubin Leonardon, Mathieu Morlier, Jérémy Lavrard-Meyer, Antoine Muller, Guillaume Fresse, Virginie Arzel, Matthieu |
| author_facet | Ribeiro, Lucas Grativol Gauthier, Lubin Leonardon, Mathieu Morlier, Jérémy Lavrard-Meyer, Antoine Muller, Guillaume Fresse, Virginie Arzel, Matthieu |
| contents | This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2404_19354 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC Ribeiro, Lucas Grativol Gauthier, Lubin Leonardon, Mathieu Morlier, Jérémy Lavrard-Meyer, Antoine Muller, Guillaume Fresse, Virginie Arzel, Matthieu Hardware Architecture Machine Learning This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board. |
| title | PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2404.19354 |