Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
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arXiv
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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866917865496510464 |
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| author | Vitolo, Paola Psaltakis, George Tomlinson, Michael Licciardo, Gian Domenico Andreou, Andreas G. |
| author_facet | Vitolo, Paola Psaltakis, George Tomlinson, Michael Licciardo, Gian Domenico Andreou, Andreas G. |
| contents | This paper investigates the use of Large Language Models (LLMs) and natural language prompts to generate hardware description code, namely Verilog. Building on our prior work, we employ OpenAI's ChatGPT4 and natural language prompts to synthesize an RTL Verilog module of a programmable recurrent spiking neural network, while also generating test benches to assess the system's correctness. The resultant design was validated in three simple machine learning tasks, the exclusive OR, the IRIS flower classification and the MNIST hand-written digit classification. Furthermore, the design was validated on a Field-Programmable Gate Array (FPGA) and subsequently synthesized in the SkyWater 130 nm technology by using an open-source electronic design automation flow. The design was submitted to Efabless Tiny Tapeout 6. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_01419 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT Vitolo, Paola Psaltakis, George Tomlinson, Michael Licciardo, Gian Domenico Andreou, Andreas G. Hardware Architecture Artificial Intelligence This paper investigates the use of Large Language Models (LLMs) and natural language prompts to generate hardware description code, namely Verilog. Building on our prior work, we employ OpenAI's ChatGPT4 and natural language prompts to synthesize an RTL Verilog module of a programmable recurrent spiking neural network, while also generating test benches to assess the system's correctness. The resultant design was validated in three simple machine learning tasks, the exclusive OR, the IRIS flower classification and the MNIST hand-written digit classification. Furthermore, the design was validated on a Field-Programmable Gate Array (FPGA) and subsequently synthesized in the SkyWater 130 nm technology by using an open-source electronic design automation flow. The design was submitted to Efabless Tiny Tapeout 6. |
| title | Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2405.01419 |