Cover Image

A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Kumar, Aman, Simon, Sebastian
Format:	Preprint
Published:	2024
Subjects:	Software Engineering Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
by: Gadde, Deepak Narayan, et al.
Published: (2024)

FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification
by: Wan, Lily Jiaxin, et al.
Published: (2026)

Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
by: Liu, Jiale, et al.
Published: (2026)

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
by: Yao, Xufeng, et al.
Published: (2024)

HW/SW Co-design of a PCM/PWM converter: a System Level Approach based in the SpecC Methodology
by: Petrini, Daniel G. P., et al.
Published: (2025)

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)

DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)

RTLSquad: Multi-Agent Based Interpretable RTL Design
by: Wang, Bowei, et al.
Published: (2025)

Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
by: Kumar, Aman, et al.
Published: (2024)

The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
by: Yang, Guang, et al.
Published: (2025)

AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
by: Zhang, Haoyi, et al.
Published: (2024)

UCAgent: An End-to-End Agent for Block-Level Functional Verification
by: Wang, Junyue, et al.
Published: (2026)

Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
by: Zou, Qingyun, et al.
Published: (2026)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
by: Dupuis, Nicolas, et al.
Published: (2025)

ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
by: Wang, Bowei, et al.
Published: (2025)

IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
by: Chen, Luanrong, et al.
Published: (2026)

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)

Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?
by: Olmos, Bryan, et al.
Published: (2024)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)

A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
by: Guo, Cong, et al.
Published: (2024)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach
by: Kumari, Suruchi, et al.
Published: (2025)

David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
by: Shankar, Shashwat, et al.
Published: (2025)

Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
by: Khan, M Zafir Sadik, et al.
Published: (2026)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecture
by: Prakash, Shvetank, et al.
Published: (2025)

Effective Design Verification -- Constrained Random with Python and Cocotb
by: Gadde, Deepak Narayan, et al.
Published: (2024)

All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
by: Gadde, Deepak Narayan, et al.
Published: (2024)

A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)

LLM-aided explanations of EDA synthesis errors
by: Qiu, Siyu, et al.
Published: (2024)

LM-Fix: Lightweight Bit-Flip Detection and Rapid Recovery Framework for Language Models
by: Tahmasivand, Ahmad, et al.
Published: (2025)

Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
by: Gadde, Deepak Narayan, et al.
Published: (2025)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
by: Bause, Oliver, et al.
Published: (2024)

CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation
by: Mi, Zhendong, et al.
Published: (2024)

FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware
by: Kang, Minwoo, et al.
Published: (2024)

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2024)