Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design
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arXiv
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| Main Authors: | Meng, Jian, Liao, Yuan, Anupreetham, Anupreetham, Hasssan, Ahmed, Yu, Shixing, Suh, Han-sok, Hu, Xiaofeng, Seo, Jae-sun |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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