Fast Algorithms for Spiking Neural Network Simulation with FPGAs
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arXiv
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866911865011961856 |
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| author | Lindqvist, Björn A. Podobas, Artur |
| author_facet | Lindqvist, Björn A. Podobas, Artur |
| contents | Using OpenCL-based high-level synthesis, we create a number of spiking neural network (SNN) simulators for the Potjans-Diesmann cortical microcircuit for a high-end Field-Programmable Gate Array (FPGA). Our best simulators simulate the circuit 25\% faster than real-time, require less than 21 nJ per synaptic event, and are bottle-necked by the device's on-chip memory. Speed-wise they compare favorably to the state-of-the-art GPU-based simulators and their energy usage is lower than any other published result. This result is the first for simulating the circuit on a single hardware accelerator. We also extensively analyze the techniques and algorithms we implement our simulators with, many of which can be realized on other types of hardware. Thus, this article is of interest to any researcher or practitioner interested in efficient SNN simulation, whether they target FPGAs or not. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2405_02019 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Fast Algorithms for Spiking Neural Network Simulation with FPGAs Lindqvist, Björn A. Podobas, Artur Neural and Evolutionary Computing Hardware Architecture Performance Using OpenCL-based high-level synthesis, we create a number of spiking neural network (SNN) simulators for the Potjans-Diesmann cortical microcircuit for a high-end Field-Programmable Gate Array (FPGA). Our best simulators simulate the circuit 25\% faster than real-time, require less than 21 nJ per synaptic event, and are bottle-necked by the device's on-chip memory. Speed-wise they compare favorably to the state-of-the-art GPU-based simulators and their energy usage is lower than any other published result. This result is the first for simulating the circuit on a single hardware accelerator. We also extensively analyze the techniques and algorithms we implement our simulators with, many of which can be realized on other types of hardware. Thus, this article is of interest to any researcher or practitioner interested in efficient SNN simulation, whether they target FPGAs or not. |
| title | Fast Algorithms for Spiking Neural Network Simulation with FPGAs |
| topic | Neural and Evolutionary Computing Hardware Architecture Performance |
| url | https://arxiv.org/abs/2405.02019 |