Evaluating LLMs for Hardware Design and Test
Fuente:
arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866912140048203776 |
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| author | Blocklove, Jason Garg, Siddharth Karri, Ramesh Pearce, Hammond |
| author_facet | Blocklove, Jason Garg, Siddharth Karri, Ramesh Pearce, Hammond |
| contents | Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to write functional code, not test code. The hardware design process consists of both design and test, and so eschewing validation and verification leaves considerable potential benefit unexplored, given that a design and test framework may allow for progress towards full automation of the digital design pipeline. In this work, we perform one of the first studies exploring how a LLM can both design and test hardware modules from provided specifications. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state-of-the-art conversational LLMs when producing Verilog for functional and verification purposes. We taped out the benchmarks on a Skywater 130nm shuttle and received the functional chip. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_02326 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Evaluating LLMs for Hardware Design and Test Blocklove, Jason Garg, Siddharth Karri, Ramesh Pearce, Hammond Hardware Architecture Artificial Intelligence Computation and Language Machine Learning Programming Languages Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to write functional code, not test code. The hardware design process consists of both design and test, and so eschewing validation and verification leaves considerable potential benefit unexplored, given that a design and test framework may allow for progress towards full automation of the digital design pipeline. In this work, we perform one of the first studies exploring how a LLM can both design and test hardware modules from provided specifications. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state-of-the-art conversational LLMs when producing Verilog for functional and verification purposes. We taped out the benchmarks on a Skywater 130nm shuttle and received the functional chip. |
| title | Evaluating LLMs for Hardware Design and Test |
| topic | Hardware Architecture Artificial Intelligence Computation and Language Machine Learning Programming Languages |
| url | https://arxiv.org/abs/2405.02326 |