Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866916236873433088 |
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| author | Sauter, Phillippe Benz, Thomas Scheffler, Paul Jiang, Zerun Muheim, Beat Gürkaynak, Frank K. Benini, Luca |
| author_facet | Sauter, Phillippe Benz, Thomas Scheffler, Paul Jiang, Zerun Muheim, Beat Gürkaynak, Frank K. Benini, Luca |
| contents | We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results (QoR), as well as an optimized physical design with an improved power grid and cell placement integration enabling a higher core utilization. The tapeout-ready version of Basilisk implemented in IHP's open 130 nm technology achieves an operation frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA design flow presented in Iguana, and a higher 55 % core utilization compared to 50 % in the baseline design. Through collaboration with EDA tool developers and domain experts, Basilisk exemplifies a synergistic effort towards competitive open-source electronic design automation (EDA) tools for research and industry applications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_03523 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC Sauter, Phillippe Benz, Thomas Scheffler, Paul Jiang, Zerun Muheim, Beat Gürkaynak, Frank K. Benini, Luca Hardware Architecture We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results (QoR), as well as an optimized physical design with an improved power grid and cell placement integration enabling a higher core utilization. The tapeout-ready version of Basilisk implemented in IHP's open 130 nm technology achieves an operation frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA design flow presented in Iguana, and a higher 55 % core utilization compared to 50 % in the baseline design. Through collaboration with EDA tool developers and domain experts, Basilisk exemplifies a synergistic effort towards competitive open-source electronic design automation (EDA) tools for research and industry applications. |
| title | Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2405.03523 |