Leveraging AES Padding: dBs for Nothing and FEC for Free in IoT Systems
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866913344872513536 |
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| author | Woo, Jongchan Vasudevan, Vipindev Adat Kim, Benjamin D. D'Oliveira, Rafael G. L. Cohen, Alejandro Stahlbuhk, Thomas Duffy, Ken R. Médard, Muriel |
| author_facet | Woo, Jongchan Vasudevan, Vipindev Adat Kim, Benjamin D. D'Oliveira, Rafael G. L. Cohen, Alejandro Stahlbuhk, Thomas Duffy, Ken R. Médard, Muriel |
| contents | The Internet of Things (IoT) represents a significant advancement in digital technology, with its rapidly growing network of interconnected devices. This expansion, however, brings forth critical challenges in data security and reliability, especially under the threat of increasing cyber vulnerabilities. Addressing the security concerns, the Advanced Encryption Standard (AES) is commonly employed for secure encryption in IoT systems. Our study explores an innovative use of AES, by repurposing AES padding bits for error correction and thus introducing a dual-functional method that seamlessly integrates error-correcting capabilities into the standard encryption process. The integration of the state-of-the-art Guessing Random Additive Noise Decoder (GRAND) in the receiver's architecture facilitates the joint decoding and decryption process. This strategic approach not only preserves the existing structure of the transmitter but also significantly enhances communication reliability in noisy environments, achieving a notable over 3 dB gain in Block Error Rate (BLER). Remarkably, this enhanced performance comes with a minimal power overhead at the receiver - less than 15% compared to the traditional decryption-only process, underscoring the efficiency of our hardware design for IoT applications. This paper discusses a comprehensive analysis of our approach, particularly in energy efficiency and system performance, presenting a novel and practical solution for reliable IoT communications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_05107 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Leveraging AES Padding: dBs for Nothing and FEC for Free in IoT Systems Woo, Jongchan Vasudevan, Vipindev Adat Kim, Benjamin D. D'Oliveira, Rafael G. L. Cohen, Alejandro Stahlbuhk, Thomas Duffy, Ken R. Médard, Muriel Emerging Technologies Hardware Architecture Systems and Control The Internet of Things (IoT) represents a significant advancement in digital technology, with its rapidly growing network of interconnected devices. This expansion, however, brings forth critical challenges in data security and reliability, especially under the threat of increasing cyber vulnerabilities. Addressing the security concerns, the Advanced Encryption Standard (AES) is commonly employed for secure encryption in IoT systems. Our study explores an innovative use of AES, by repurposing AES padding bits for error correction and thus introducing a dual-functional method that seamlessly integrates error-correcting capabilities into the standard encryption process. The integration of the state-of-the-art Guessing Random Additive Noise Decoder (GRAND) in the receiver's architecture facilitates the joint decoding and decryption process. This strategic approach not only preserves the existing structure of the transmitter but also significantly enhances communication reliability in noisy environments, achieving a notable over 3 dB gain in Block Error Rate (BLER). Remarkably, this enhanced performance comes with a minimal power overhead at the receiver - less than 15% compared to the traditional decryption-only process, underscoring the efficiency of our hardware design for IoT applications. This paper discusses a comprehensive analysis of our approach, particularly in energy efficiency and system performance, presenting a novel and practical solution for reliable IoT communications. |
| title | Leveraging AES Padding: dBs for Nothing and FEC for Free in IoT Systems |
| topic | Emerging Technologies Hardware Architecture Systems and Control |
| url | https://arxiv.org/abs/2405.05107 |