MEIC: Re-thinking RTL Debug Automation using LLMs
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866910442913267712 |
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| author | Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe |
| author_facet | Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe |
| contents | The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://anonymous.4open.science/r/Verilog-Auto-Debug-6E7F/. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_06840 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | MEIC: Re-thinking RTL Debug Automation using LLMs Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe Hardware Architecture Software Engineering The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://anonymous.4open.science/r/Verilog-Auto-Debug-6E7F/. |
| title | MEIC: Re-thinking RTL Debug Automation using LLMs |
| topic | Hardware Architecture Software Engineering |
| url | https://arxiv.org/abs/2405.06840 |